1.8 Volt Intel
Wireless Flash Memory with 3 Volt I/O
Datasheet
23
The read-status mode supports single synchronous and single asynchronous reads only; it doesn’t
support burst reads. The first falling edge of OE# or CE# latches and updates status register data.
The operation doesn’t affect other partitions’ modes. Because the status register is 8 bits wide, only
DQ [7:0] contains valid status register data; DQ [15:8] contains zeros. See
Table 8, “Status
Register Definitions” on page 23
and
Table 9, “Status Register Descriptions” on page 23
.
Each 4-Mbit partition contains its own status register. Bits SR[6:0] are unique to each partition, but
SR[7], the Device WSM Status (DWS) bit, pertains to the entire device. SR[7] provides program
and erase status of the entire device. By contrast, the Partition WSM Status (PWS) bit, SR[0],
provides program and erase status of the
addressed partition
only. Status register bits SR[6:1]
present information about partition-specific program, erase, suspend, V
PP
, and block-lock states.
Table 10, “Status Register Device WSM and Partition Write Status Description” on page 24
presents descriptions of DWS (SR[7]) and PWS (SR[0]) combinations.
Table 8.
Status Register Definitions
DWS
ESS
ES
PS
VPPS
PSS
DPS
PWS
7
6
5
4
3
2
1
0
Table 9.
Status Register Descriptions
Bit
Name
State
Description
7
DWS
Device WSM Status
0 = Device WSM is Busy
1 = Device WSM is Ready
SR[7] indicates erase or program completion in the
device. SR[6:1] are invalid while SR[7] = 0. See
Table
10
for valid SR[7] and SR[0] combinations.
6
ESS
Erase Suspend Status
0 = Erase in progress/completed
1 = Erase suspended
After issuing an Erase Suspend command, the WSM
halts and sets SR[7] and SR[6]. SR[6] remains set until
the device receives an Erase Resume command.
5
ES
Erase Status
0 = Erase successful
1 = Erase error
SR[5] is set if an attempted erase failed. A Command
Sequence Error is indicated when SR[7,5:4] are set.
4
PS
Program Status
0 = Program successful
1 = Program error
SR[4] is set if the WSM failed to program a word.
3
VPPS
VPP Status
0 = V
PP
OK
1 = V
PP
low detect, operation aborted
The WSM indicates the V
PP
level after program or
erase completes. SR[3] does not provide continuous
V
PP
feedback and isn’t guaranteed when V
PP
≠
V
PP1/2
.
2
PSS
Program Suspend
Status
0 = Program in progress/completed
1 = Program suspended
After receiving a Program Suspend command, the
WSM halts execution and sets SR[7] and SR[2]. They
remain set until a Resume command is received.
1
DPS
Device Protect Status
0 = Unlocked
1 = Aborted erase/program attempt on
locked block
If an erase or program operation is attempted to a
locked block (if WP# = V
IL
), the WSM sets SR[1] and
aborts the operation.
0
PWS
Partition Write Status
0 = This partition is busy, but only if
SR[7]=0
1 = Another partition is busy, but only if
SR[7]=0
Addressed partition is erasing or programming. In EFP
mode, SR[0] indicates that a data-stream word has
finished programming or verifying depending on the
particular EFP phase. See
Table 10
for valid SR[7] and
SR[0] combinations.