參數資料
型號: LH28F320S5H-L
廠商: Sharp Corporation
英文描述: 32M-BIT ( 2Mbit x16 / 4Mbit x8 )Boot Block Flash MEMORY(32M位( 2M位 x16 / 4M位 x8 )Boot Block 閃速存儲器)
中文描述: 32兆位(2Mbit的x16 /的4Mb × 8)啟動塊閃存(32兆位(200萬位x16 / 4分位× 8)啟動塊閃速存儲器)
文件頁數: 10/50頁
文件大小: 338K
代理商: LH28F320S5H-L
- 10 -
3.6
Query Operation
The query operation outputs the query structure.
Query database is stored in the 48-byte ROM.
Query structures allows system software to gain
critical information for controlling the flash
Reserved for
Future Implementation
Block 63 Status Code
Block 63
Block 1
Block 0
(Blocks 2 through 62)
Reserved for
Future Implementation
Reserved for
Future Implementation
Block 1 Status Code
Reserved for
Future Implementation
Reserved for
Future Implementation
Block 0 Status Code
Device Code
Manufacture Code
3FFFFF
3F0006
3F0005
3F0004
3F0003
3F0000
3EFFFF
020000
01FFFF
010006
010005
010004
010003
010000
00FFFF
000006
000005
000004
000003
000002
000001
000000
LH28F320S5-L/S5H-L
3.5
The read identifier codes operation outputs the
manufacture code, device code, block status codes
for each block (see
Fig. 2
). Using the manufacture
and device codes, the system CPU can
automatically match the device with its proper
algorithms. The block status codes identify locked
or unlocked block setting and erase completed or
erase uncompleted condition.
Read Identifier Codes Operation
Fig. 2 Device Identifier Code Memory Map
component. Query structures are always presented
on the lowest-order data output (DQ
0
-DQ
7
) only.
3.7
Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register. When
V
CC
= V
CC1/2
and V
PP
= V
PPH1
, the CUI additionally
controls block erase, full chip erase, (multi)
word/byte write and block lock-bit configuration.
Write
The Block Erase command requires appropriate
command data and an address within the block to
be erased. The Word/Byte Write command requires
the command and address of the location to be
written. Set Block Lock-Bit command requires the
command and block address within the device
(Block Lock) to be locked. The Clear Block Lock-
Bits command requires the command and address
within the device.
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are
active. The address and data needed to execute a
command are latched on the rising edge of WE# or
CE# (whichever goes high first). Standard
microprocessor write timings are used.
Fig. 17
and
Fig. 18
illustrate WE# and CE#-controlled write
operations.
4 COMMAND DEFINITIONS
When the V
PP
voltage
V
PPLK
, read operations
from the status register, identifier codes, query, or
blocks are enabled. Placing V
PPH1
on V
PP
enables
successful block erase, full chip erase, (multi)
word/byte write and block lock-bit configuration
operations.
Device operations are selected by writing specific
commands into the CUI.
Table 3
defines these
commands.
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