參數(shù)資料
型號： LH28F320S5H-L
廠商： Sharp Corporation
英文描述： 32M-BIT ( 2Mbit x16 / 4Mbit x8 )Boot Block Flash MEMORY(32M位( 2M位 x16 / 4M位 x8 )Boot Block 閃速存儲器)
中文描述： 32兆位（2Mbit的x16 /的4Mb × 8）啟動(dòng)塊閃存（32兆位（200萬位x16 / 4分位× 8）啟動(dòng)塊閃速存儲器）
文件頁數(shù)： 12/50頁
文件大?。?/td> 338K
代理商： LH28F320S5H-L
goes high first).
ID = Data read from identifier codes.
QD = Data read from query database.
Following the Read Identifier Codes command, read
operations access manufacture, device and block status
codes. See
Section 4.2
for read identifier code data.
LH28F320S5-L/S5H-L
- 12 -
Table 3 Command Definitions
(NOTE 10)
BUS CYCLES
NOTE
REQ
’
D.
Oper
(NOTE 1)
Addr
(NOTE 2)
Data
(NOTE 3)
Oper
(NOTE 1)
Addr
(NOTE 2)
Data
(NOTE 3)
1
Write
X
≥
2
4
Write
X
≥
2
Write
X
2
Write
X
2
5
Write
BA
2
Write
X
2
5, 6
Write
WA
NOTES :
1.
Bus operations are defined in
Table 2.1
and
Table 2.2
.
2.
X = Any valid address within the device.
IA = Identifier code address : see
Fig. 2
.
QA = Query offset address.
BA = Address within the block being erased or locked.
WA = Address of memory location to be written.
3.
SRD = Data read from status register. See
Table 13.1
for a description of the status register bits.
WD = Data to be written at location WA. Data is latched
4.
5.
If the block is locked, WP# must be at V
IH
to enable
block erase or (multi) word/byte write operations.
Attempts to issue a block erase or (multi) word/byte write
to a locked block while RP# is V
IH
.
Either 40H or 10H is recognized by the WSM as the
byte write setup.
A block lock-bit can be set while WP# is V
IH
.
WP# must be at V
IH
to clear block lock-bits. The clear
block lock-bits operation simultaneously clears all block
lock-bits.
Following the Third Bus Cycle, inputs the write address
and write data of "N" times. Finally, input the confirm
command "D0H".
10. Commands other than those shown above are reserved
by SHARP for future device implementations and should
not be used.
6.
7.
8.
9.
COMMAND
FIRST BUS CYCLE
SECOND BUS CYCLE
Read Array/Reset
Read Identifier Codes
Query
Read Status Register
Clear Status Register
Block Erase Setup/Confirm
Full Chip Erase Setup/Confirm
Word/Byte Write Setup/Write
Alternate Word/Byte Write
Setup/Write
Multi Word/Byte Write
Setup/Confirm
Block Erase and (Multi)
Word/Byte Write Suspend
Confirm and Block Erase and
(Multi) Word/Byte Write Resume
Block Lock-Bit Set
Setup/Confirm
Block Lock-Bit Reset
Setup/Confirm
STS Configuration
Level-Mode for Erase
and Write (RY/BY# Mode)
STS Configuration
Pulse-Mode for Erase
STS Configuration
Pulse-Mode for Write
STS Configuration Pulse-Mode
for Erase and Write
FFH
90H
98H
70H
50H
20H
30H
40H
Read
Read
Read
IA
QA
X
ID
QD
SRD
Write
Write
Write
BA
X
WA
D0H
D0H
WD
2
5, 6
Write
WA
10H
Write
WA
WD
≥
4
9
Write
WA
E8H
Write
WA
N
–
1
1
5
Write
X
B0H
1
5
Write
X
D0H
2
7
Write
BA
60H
Write
BA
01H
2
8
Write
X
60H
Write
X
D0H
2
Write
X
B8H
Write
X
00H
2
Write
X
B8H
Write
X
01H
2
Write
X
B8H
Write
X
02H
2
Write
X
B8H
Write
X
03H
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