參數(shù)資料
型號: LH28F320S5H-L
廠商: Sharp Corporation
英文描述: 32M-BIT ( 2Mbit x16 / 4Mbit x8 )Boot Block Flash MEMORY(32M位( 2M位 x16 / 4M位 x8 )Boot Block 閃速存儲器)
中文描述: 32兆位(2Mbit的x16 /的4Mb × 8)啟動塊閃存(32兆位(200萬位x16 / 4分位× 8)啟動塊閃速存儲器)
文件頁數(shù): 42/50頁
文件大?。?/td> 338K
代理商: LH28F320S5H-L
- 42 -
full chip erase, (multi) word/byte write or block lock-bit
configuration.
V
PP
should be held at V
PPH1
until determination of block
erase, full chip erase, (multi) word/byte write or block
lock-bit configuration success (SR.1/3/4/5 = 0).
SYMBOL
t
AVAV
PARAMETER
NOTE
MIN.
90
MAX.
MIN.
100
MAX.
MIN.
120
MAX.
Write Cycle Time
RP# High Recovery to WE#
Going Low
CE# Setup to WE# Going Low
WE# Pulse Width
WP# V
IH
Setup to WE#
Going High
V
PP
Setup to WE# Going High
Address Setup to WE#
Going High
Data Setup to WE# Going High
Data Hold from WE# High
Address Hold from WE# High
CE# Hold from WE# High
WE# Pulse Width High
WE# High to STS Going Low
Write Recovery before Read
V
PP
Hold from Valid SRD,
STS High Z
WP# V
IH
Hold from Valid SRD,
STS High Z
NOTES :
1.
Read timing characteristics during block erase, full chip
erase, (multi) word/byte write and block lock-bit
configuration operations are the same as during read-
only operations. Refer to
Section 6.2.4
Characteristics
"
for read-only operations.
2.
Sampled, not 100% tested.
3.
Refer to
Table 3
for valid A
IN
and D
IN
for block erase,
ns
t
PHWL
2
1
1
1
μs
t
ELWL
t
WLWH
10
40
10
40
10
40
ns
ns
t
SHWH
2
100
100
100
ns
t
VPWH
2
100
100
100
ns
t
AVWH
3
40
40
40
ns
t
DVWH
t
WHDX
t
WHAX
t
WHEH
t
WHWL
t
WHRL
t
WHGL
3
40
5
5
10
30
40
5
5
10
30
40
5
5
10
30
ns
ns
ns
ns
ns
ns
ns
90
90
90
0
0
0
t
QVVL
2, 4
0
0
0
ns
t
QVSL
2, 4
0
0
0
ns
LH28F320S5-L/S5H-L
6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS
(NOTE 1)
V
CC
= 5.0±0.25V, 5.0±0.5 V, T
A
= 0 to +70
C or
40 to +85°C
VERSIONS
V
CC
±0.25 V
V
CC
±0.5 V
(NOTE 5)
LH28F320S5-L90
LH28F320S5H-L90
(NOTE 6)
LH28F320S5-L12
LH28F320S5H-L12
(NOTE 6)
LH28F320S5-L90
LH28F320S5H-L90
UNIT
"
AC
4.
5.
See
Fig. 12
"
Transient Input/Output Reference
Waveform
"
and
Fig. 14
"
Transient Equivalent Testing
Load Circuit
"
(High Speed Configuration) for testing
characteristics.
See
Fig. 13
"
Transient Input/Output Reference
Waveform
"
and
Fig. 14
"
Transient Equivalent Testing
Load Circuit
"
(Standard Configuration) for testing
characteristics.
6.
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