參數(shù)資料
型號(hào): LH28F320S5H-L
廠商: Sharp Corporation
英文描述: 32M-BIT ( 2Mbit x16 / 4Mbit x8 )Boot Block Flash MEMORY(32M位( 2M位 x16 / 4M位 x8 )Boot Block 閃速存儲(chǔ)器)
中文描述: 32兆位(2Mbit的x16 /的4Mb × 8)啟動(dòng)塊閃存(32兆位(200萬位x16 / 4分位× 8)啟動(dòng)塊閃速存儲(chǔ)器)
文件頁數(shù): 6/50頁
文件大?。?/td> 338K
代理商: LH28F320S5H-L
- 6 -
LH28F320S5-L/S5H-L
block erase, full chip erase, (multi) word/byte write
or block lock-bit configuration. STS High Z indicates
that the WSM is ready for a new command, block
erase is suspended and (multi) word/byte write are
inactive, (multi) word/byte write are suspended, or
the device is in deep power-down mode. The other
3 alternate configurations are all pulse mode for
use as a system interrupt.
The access time is 90 ns (t
AVQV
) at the V
CC
supply voltage range of 4.75 to 5.25 V over the
temperature range, 0 to +70°C (LH28F320S5-L)/
–40 to +85°C (LH28F320S5H-L). At 4.5 to 5.5 V
V
CC
, the access time is 100 ns or 120 ns.
The Automatic Power Saving (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical I
CCR
current is 1 mA at
5 V V
CC
.
When either CE
0
# or CE
1
#, and RP# pins are at
V
CC
, the I
CC
CMOS standby mode is enabled.
When the RP# pin is at GND, deep power-down
mode is enabled which minimizes power
consumption and provides write protection during
reset. A reset time (t
PHQV
) is required from RP#
switching high until outputs are valid. Likewise, the
device has a wake time (t
PHEL
) from RP#-high until
writes to the CUI are recognized. With RP# at
GND, the WSM is reset and the status register is
cleared.
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