參數(shù)資料
型號(hào): LH28F320S5H-L
廠商: Sharp Corporation
英文描述: 32M-BIT ( 2Mbit x16 / 4Mbit x8 )Boot Block Flash MEMORY(32M位( 2M位 x16 / 4M位 x8 )Boot Block 閃速存儲(chǔ)器)
中文描述: 32兆位(2Mbit的x16 /的4Mb × 8)啟動(dòng)塊閃存(32兆位(200萬(wàn)位x16 / 4分位× 8)啟動(dòng)塊閃速存儲(chǔ)器)
文件頁(yè)數(shù): 44/50頁(yè)
文件大小: 338K
代理商: LH28F320S5H-L
- 44 -
erase, full chip erase, (multi) word/byte write or block
lock-bit configuration success (SR.1/3/4/5 = 0).
SYMBOL
t
AVAV
PARAMETER
NOTE
MIN.
90
MAX.
MIN.
100
MAX.
MIN.
120
MAX.
Write Cycle Time
RP# High Recovery to CE#
Going Low
WE# Setup to CE# Going Low
CE# Pulse Width
WP# V
IH
Setup to CE# Going High
V
PP
Setup to CE# Going High
Address Setup to CE# Going High
Data Setup to CE# Going High
Data Hold from CE# High
Address Hold from CE# High
WE# Hold from CE# High
CE# Pulse Width High
CE# High to STS Going Low
Write Recovery before Read
V
PP
Hold from Valid SRD,
STS High Z
WP# V
IH
Hold from Valid SRD,
STS High Z
NOTES :
1.
In systems where CE# defines the write pulse width
(within a longer WE# timing waveform), all setup, hold
and inactive WE# times should be measured relative to
the CE# waveform.
2.
Sampled, not 100%tested.
3.
Refer to
Table 3
for valid A
IN
and D
IN
for block erase,
full chip erase, (multi) word/byte write or block lock-bit
configuration.
4.
V
PP
should be held at V
PPH1
until determination of block
ns
t
PHEL
2
1
1
1
μs
t
WLEL
t
ELEH
t
SHEH
t
VPEH
t
AVEH
t
DVEH
t
EHDX
t
EHAX
t
EHWH
t
EHEL
t
EHRL
t
EHGL
0
50
100
100
40
40
5
5
0
25
0
50
100
100
40
40
5
5
0
25
0
50
100
100
40
40
5
5
0
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
2
3
3
90
90
90
0
0
0
t
QVVL
2, 4
0
0
0
ns
t
QVSL
2, 4
0
0
0
ns
LH28F320S5-L/S5H-L
6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES
(NOTE 1)
V
CC
= 5.0±0.25 V, 5.0±0.5V, T
A
= 0 to +70
C or
40 to +85°C
VERSIONS
V
CC
±0.25 V
V
CC
±0.5 V
(NOTE 5)
LH28F320S5-L90
LH28F320S5H-L90
(NOTE 6)
LH28F320S5-L12
LH28F320S5H-L12
(NOTE 6)
LH28F320S5-L90
LH28F320S5H-L90
UNIT
5.
See
Fig. 12
"
Transient Input/Output Reference
Waveform
"
and
Fig. 14
"
Transient Equivalent Testing
Load Circuit
"
(High Speed Configuration) for testing
characteristics.
See
Fig. 13
"
Transient Input/Output Reference
Waveform
"
and
Fig. 14
"
Transient Equivalent Testing
Load Circuit
"
(Standard Configuration) for testing
characteristics.
6.
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