參數(shù)資料
型號： M30100
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述： 單片16位CMOS微機
文件頁數(shù)： 112/164頁
文件大?。?/td> 3302K
代理商： M30100
deveopment
A-D Converter
Tentative Specifications REV.E1
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
111
A-D Converter
The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive
coupling amplifier. Pins P0
0
to P0
7
, P1
0
to P1
3
, P4
0
and P4
1
also function as the analog signal input pins.
The direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit
(bit 5 at address 00D7
16
) can be used to isolate the resistance ladder of the A-D converter from the refer-
ence voltage input pin (V
REF
) when the A-D converter is not used. Doing so stops any current flowing into
the resistance ladder from V
REF
, reducing the power dissipation. When using the A-D converter, start A-D
conversion only after connecting to V
REF
.
The result of A-D conversion is stored in the A-D registers. When set to 10-bit precision, the low 8 bits are
stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low
8 bits are stored in the even addresses.
Table 1.16.1 shows the performance of the A-D converter. Figure 1.16.1 shows the block diagram of the A-
D converter, and Figures 1.16.2 and 1.16.3 show the A-D converter-related registers.
Table 1.16.1. Performance of A-D converter
Item
Method of A-D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1)
0V to V
CC
Operating clock
φ
AD
(Note 2)
V
CC
= 5V
f
AD
, divide-by-2 of f
AD
, divide-by-4 of f
AD
, f
AD
=f(X
IN
)
V
CC
= 3V
divide-by-2 of f
AD
, divide-by-4 of f
AD
, f
AD
=f(X
IN
)
Resolution
8-bit or 10-bit (selectable)
Absolute precision
V
CC
= 5V
Without sample and hold function
±
3LSB
With sample and hold function (8-bit resolution)
±
2LSB
With sample and hold function (10-bit resolution)
AN
0
to AN
11
input :
±
3LSB
ANEX
0
and ANEX
1
input (including mode in which external
operation amp is connected) :
±
7LSB
V
CC
= 3V
Without sample and hold function (8-bit resolution)
±
2LSB
Operating modes
One-shot mode and repeat mode (Note 3)
Analog input pins
12 pins (AN
0
to AN
11
) + 2 pins (ANEX
0
to ANEX
1
)
A-D conversion start condition
Software trigger
A-D conversion starts when the A-D conversion start flag changes to “1”
Conversion speed per pin Without sample and hold function
8-bit resolution: 49
φ
AD
cycles
,
10-bit resolution: 59
φ
AD
cycles
With sample and hold function
8-bit resolution: 28
φ
AD
cycles
,
10-bit resolution: 33
φ
AD
cycles
Note 1: Does not depend on use of sample and hold function.
Note 2: Divide f
AD
if (X
IN
) exceeds 10MHz, and make
φ
AD
equal to or lower than 10MHz. Also if Vcc is less
than 4.2V or an external RC circuit is used for the main clock, divide f
AD
and make
φ
AD
equal to or
lower than f
AD
/2.
Without sample and hold function, set the
φ
AD frequency to 250kHz min.
With the sample and hold function, set the
φ
AD frequency to 1MHz min.
Note 3: In repeat mode, only 8-bit mode can be used.
Performance
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