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參數(shù)資料
| 型號(hào)： | M30100 |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單片16位CMOS微機(jī) |
| 文件頁數(shù)： | 26/164頁 |
| 文件大?。?/td> | 3302K |
| 代理商： | M30100 |
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deveopment
Status Transition of BCLK
Tentative Specifications REV.E1
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
25
Status Transition of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
BCLK. Table 1.8.4 shows the operating modes corresponding to the settings of system clock control
registers 0 and 1.
When reset, division by 8 mode is set. The main clock division select bit 0 (bit 6 at address 0006
16
)
changes to “1” when shifting from high-speed/medium-speed mode to stop mode or at a reset. The follow-
ing shows the operational modes of BCLK. When shifting from low-speed/low power dissipation mode to
stop mode, the value before stop mode is retained.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. Before the user can go from this mode to no division
mode, division by 2 mode, or division by 4 mode, the main clock must be oscillating stably. When going to
low-speed or lower power dissipation mode, sure the sub-clock is oscillating stably.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(5) No-division mode
The main clock is divided by 1 to obtain the BCLK. When using an external RC circuit for the main clock,
no-division mode must not be used.
(6) Low-speed mode
f
C
is used as BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before
transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub-
clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately
after powering up and after stop mode is cancelled.
(7) Low power dissipation mode
f
C
is the BCLK and the main clock is stopped.
(8) Ring oscillator mode
This mode sets the ring oscillator as BCLK. The same as when X
IN
is the main clock, the modes are no
division, 2-division, 4-division, 8-division, and 16-division.
Note: Before the count source for BCLK can be changed from X
IN
to XC
IN
or vice versa, the clock to which
the count source is going to be switched must be oscillating stably. Allow a wait time in software for
the oscillation to stabilize before switching over the clock.
And, be sure to shift from division by 8 mode when you change it to ring oscillator mode. Shift to
other mode after you surely shift to the mode for division by 8 mode when you change it from ring
oscillator mode to other mode.
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| M30-1000046 | 功能描述:集管和線殼 FEMALE CRIMP CONTACT 1.25MM PTCH 20K REEL RoHS:否 產(chǎn)品種類:1.0MM Rectangular Connectors 產(chǎn)品類型:Headers - Pin Strip 系列:DF50 觸點(diǎn)類型:Pin (Male) 節(jié)距:1 mm 位置/觸點(diǎn)數(shù)量:16 排數(shù):1 安裝風(fēng)格:SMD/SMT 安裝角:Right 端接類型:Solder 外殼材料:Liquid Crystal Polymer (LCP) 觸點(diǎn)材料:Brass 觸點(diǎn)電鍍:Gold 制造商:Hirose Connector |
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