參數(shù)資料
型號: M30100
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述: 單片16位CMOS微機(jī)
文件頁數(shù): 18/164頁
文件大?。?/td> 3302K
代理商: M30100
deveopment
Tentative Specifications REV.E1
SFR
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
17
0080
16
0081
16
0082
16
0083
16
0084
16
0085
16
0086
16
0087
16
0088
16
0089
16
008A
16
008B
16
008C
16
008D
16
008E
16
008F
16
0090
16
0091
16
0092
16
0093
16
0094
16
0095
16
0096
16
0097
16
0098
16
0099
16
009A
16
009B
16
009C
16
009D
16
009E
16
009F
16
00A0
16
00A1
16
00A2
16
00A3
16
00A4
16
00A5
16
00A6
16
00A7
16
00A8
16
00A9
16
00AA
16
00AB
16
00AC
16
00AD
16
00AE
16
00AF
16
00B0
16
00B1
16
00B2
16
00B3
16
00B4
16
00B5
16
00B6
16
00B7
16
00B8
16
00B9
16
00BA
16
00BB
16
00BC
16
00BD
16
00BE
16
00BF
16
Timer Y, Z mode register (TYZMR)
Prescaler Y (PREY)
Timer Y secondary (TYSC)
Timer Y primary (TYPR)
External input enable register (INTEN)
Key input enable register (KIEN)
Timer C control register 1 (TCC1)
Time measurement register (TM)
Timer Y, Z waveform output control register (PUM)
Prescaler Z (PREZ)
Timer C control register 0 (TCC0)
UART0 transmit/receive mode register (U0MR)
UART0 bit rate generator (U0BRG)
UART0 transmit buffer register (U0TB)
UART0 receive buffer register (U0RB)
UART1 transmit/receive mode register (U1MR)
UART1 bit rate generator (U1BRG)
UART1 transmit buffer register (U1TB)
UART1 receive buffer register (U1RB)
UART0 transmit/receive control register 0 (U0C0)
UART0 transmit/receive control register 1 (U0C1)
UART1 transmit/receive control register 0 (U1C0)
UART1 transmit/receive control register 1 (U1C1)
UART transmit/receive control register 2 (UCON)
Timer Z secondary (TZSC)
Timer Z primary (TZPR)
Prescaler 1 (PRE1)
Timer 1 (T1)
Timer X mode register (TXMR)
Prescaler X (PREX)
Timer X (TX)
Timer count source set register (TCSS)
Clock prescaler reset flag (CPSRF)
Timer Y, Z output control register (TYZOC)
Timer C counter (TC)
00C0
16
00C1
16
00C2
16
00C3
16
00C4
16
00C5
16
00C6
16
00C7
16
00C8
16
00C9
16
00CA
16
00CB
16
00CC
16
00CD
16
00CE
16
00CF
16
00D0
16
00D1
16
00D2
16
00D3
16
00D4
16
00D5
16
00D6
16
00D7
16
00D8
16
00D9
16
00DA
16
00DB
16
00DC
16
00DD
16
00DE
16
00DF
16
00E0
16
00E1
16
00E2
16
00E3
16
00E4
16
00E5
16
00E6
16
00E7
16
00E8
16
00E9
16
00EA
16
00EB
16
00EC
16
00ED
16
00EE
16
00EF
16
00F0
16
00F1
16
00F2
16
00F3
16
00F4
16
00F5
16
00F6
16
00F7
16
00F8
16
00F9
16
00FA
16
00FB
16
00FC
16
00FD
16
00FE
16
00FF
16
A-D register (AD)
Port P0 (P0)
Port P1 (P1)
Port P0 direction register (PD0)
Port P1 direction register (PD1)
Port P2 (P2)
Port P3 (P3)
Port P2 direction register (PD2)
Port P3 direction register (PD3)
Port P4 (P4)
Port P4 direction register (PD4)
Pull-up control register 0 (PUR0)
Pull-up control register 1 (PUR1)
Port P1 drive capacity control register (DRR)
A-D control register 0 (ADCON0)
A-D control register 1 (ADCON1)
D-A register (DA)
A-D control register 2 (ADCON2)
D-A control register (DACON)
Figure 1.6.2. Location of peripheral unit control registers (2)
Note: The blank area is reserved and must not be read or written.
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