參數(shù)資料
型號: M30100
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述: 單片16位CMOS微機
文件頁數(shù): 67/164頁
文件大?。?/td> 3302K
代理商: M30100
deveopment
Tentative Specifications REV.E1
Timer X
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
66
(3) Event counter mode
In this mode, the timer counts an external signal fed to CNTR0 pin. (See Table 1.14.5) Figure 1.14.8
shows Timer X mode register in event counter mode.
Item
Specification
Count source
Count operation
External signals fed to CNTR
0
pin (Active edge is selected by software)
Down count
When the timer underflows, it reloads the reload register contents before continuing
counting
1/(n+1)/(m+1) n : Set value of Prescaler X, m: Set value of Timer X
Count start flag is set (=1)
Count start flag is reset (=0)
Interrupt request generation timing
When Timer X underflows [Timer X interruption]
Rising (R0EDG=0) or falling (R0EDG=1) of CNTR0 input [CNTR0 interruption]
CNTR0 pin function
Count source input
TX
OUT
pin function
Programmable I/O port
Read from timer
Count value can be read out by reading Timer X register.
Same applies to Prescaler X register.
Write to timer
When a value is written to Timer X register, it is written to both reload register and counter.
Same applies to Prescaler X register.
Select function
CNTR0 polarity switching function
The active edge of count source can be selected to be the rising or the falling edge with
software.
Divide ratio
Count start condition
Count stop condition
Timer X mode register
Symbol
TXMR
Address
008B
16
When reset
00000000
2
Bit name
Function
Bit symbol
b7
b6 b5
b4
0
b3
b2
b1 b0
1
b1 b0
TXMOD2
TXS
TXMOD1
R0EDG
TXMOD0
TXOCNT
CNTR0 polarity
switching bit
Operation mode
select bit 0, 1
AA
AA
AA
AA
AA
AA
AA
0: Counts at rising edge (Interrupt at rising edge)
1: Counts at falling edge(Interrupt at falling edge)
Timer X count
start flag
0 : Stops counting
1 : Starts counting
0 : Set to "0" in event counter mode
AA
AA
0
0
0 : Set to "0" in event counter mode
(Note 1)
Note 1: This bit should rewrite with inhibiting the CNTR0 interrupt.
Invalid in event counter mode.
When write, set "0". When read, this contents is indeteminate.
TXEDG
TXUND
Invalid in event counter mode.
When write, set "0". When read, this contents is indeteminate.
Figure 1.14.8. Timer X mode register in event counter mode
Table 1.14.5. Specifications of event counter mode
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