參數(shù)資料
型號(hào): M30100
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述: 單片16位CMOS微機(jī)
文件頁數(shù): 19/164頁
文件大?。?/td> 3302K
代理商: M30100
Bus Control
deveopment
Tentative Specifications REV.E1
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
18
Bus Control
During access, the memory areas (ROM, RAM, FLASH, etc.) and the SFR area have different bus cycles.
As shown in Table 1.7.1, memory areas can be accessed in one cycle of the CPU operation clock BCLK.
The SFR area can be accessed in two cycles of BCLK.
The memory areas and the SFR area also have different bus widths. The memory areas have a 16-bit bus
width, while the SFR area has an 8-bit bus width. Consequently, different operations are used when the
areas are accessed in word (16 bits) units. Table 1.7.2 shows the bus cycles that are necessary to access
the SFR area and the memory areas.
Area
Even address
byte access
BCLK
Data
BCLK
BCLK
BCLK
Address
BCLK
BCLK
BCLK
BCLK
Address
SFR area
Memory area
Even
Odd
Data
Data
Data
Data
Word
Data
Data
Data
Data
Data
Data
Data
Odd
Odd
Odd+1
Odd
Odd+1
Even
Even
Even+1
Even/even+1
Data
Address
Data
Address
Data
Address
Data
Address
Data
Data
Address
Data
Address
Add address
byte access
Even address
word access
Add address
word access
00000
16
XXXXX
16
FFFFF
16
00400
16
Internal RAM area
YYYYY
16
Internal ROM area
SFR area
(For details, see
Figures 1.6.1 and 1.
6.2)
SFR area
Memory area
Table 1.7.1. Bus cycles for access areas
Area Bus cycle
SFR
Internal ROM/RAM
2 BCLK cycles
1 BCLK cycles
Figure 1.7.1. SFR area and memory areas
Table 1.7.2. Cycles for access areas
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