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參數(shù)資料
| 型號： | M30100 |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單片16位CMOS微機(jī) |
| 文件頁數(shù)： | 58/164頁 |
| 文件大?。?/td> | 3302K |
| 代理商： | M30100 |
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deveopment
Tentative Specifications REV.E1
Watchdog Timer
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
57
Figure 1.13.1. Block diagram of watchdog timer
Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. Therefore, we recom-
mend using the watchdog timer to improve reliability of a system. The watchdog timer is a 15-bit counter
which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog timer interrupt
or reset is generated when an underflow occurs in the watchdog timer. A watchdog timer interrupt or reset
is selected by bit 2 of the processor mode register 1. When X
IN
is selected for the BCLK, bit 7 of the
watchdog timer control register (address 000F
16
) selects the prescaler division ratio (by 16 or by 128).
When X
CIN
is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7 of the watchdog
timer control register (address 000F
16
).
When X
IN
is selected in BCLK
Watchdog timer cycle =
When X
CIN
is selected in BCLK
Watchdog timer cycle =
For example, when BCLK is 10MHz and the prescaler division ratio is set to 16, the watchdog timer cycle is
approximately 52.4 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E
16
) and when
a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E
16
).
Figure 1.13.1 shows the block diagram of the watchdog timer. Figure 1.13.2 shows the watchdog timer-
related registers.
Write to the watchdog timer
start register
(address 000E
16
)
RESET
"PM12=0"
Watchdog timer
interrupt request
Watchdog timer
Set to
“7FFF
16
”
1/128
1/16
“CM07 = 0”
“WDC7 = 1”
“CM07 = 0”
“WDC7 = 0”
“CM07 = 1”
BCLK
1/2
Prescaler
"PM12=1"
Reset
Prescaler division ratio (16 or 128) x watchdog timer count (32768)
BCLK
Prescaler division ratio (2) x watchdog timer count (32768)
BCLK
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