參數(shù)資料
型號： M30100
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述： 單片16位CMOS微機
文件頁數(shù)： 130/164頁
文件大?。?/td> 3302K
代理商： M30100
deveopment
Tentative Specifications REV.E1
Usage precaution
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
129
Stop Mode
(1) After returning from stop mode, an unexpected operation may occur (for example, undefined instruction
interrupt, BRK instruction interrupt, etc.).
Execute a JMP.B instruction after an instruction to write data to the all clock stop control bit. A program
example is described as follows:
MOV.B:S
JMP.B
#21H, CM1 ; writing to the all clock stop control bit to “1”(stop mode)
L1
L1 :
NOP
NOP
NOP
NOP
Interrupts
(1) Reading Address 0 by Firmware
Please do not read address 0 by firmware. In the CPU's interrupt processing sequence, when a
maskable interrupt occurs, the interrupt information (interrupt no. and interrupt request level) are read
from address 0. This read in turn, clears the interrupt request bit to "0" even pending with higher request
level. Reading address 0 by firmware may cause interrupt cancellation or unexpected interrupts so
please do not read address 0 by firmware.
(2) Stack Pointer
Set the value of the stack pointer before accepting interrupts. Immediately after a reset, the value of the
stack pointer is 0000
16
. Accepting an interrupt before setting a value of the stack pointer may produce
unpredictable results (runaway program, etc.) Make sure that you set the value of the stack pointer
before accepting interrupts.
(3) External interrupts
Clear the interrupt request bit to "0" when the INT0 - INT3 polarity is changed. The reason being is that
an interrupt request may be generated when the polarity is changed.
(4) Rewriting the Interrupt Control Register
When rewriting the Interrupt Control Register, do it at a point where it does not generate an interrupt
request for that register. If there is a possibility that an interrupt may occur, disable the interrupt before
rewriting. Examples are shown below.
Example 1:
INT_SWITCH1:
FCLR
AND.B
NOP
NOP
FSET
I
#00h, 0055h
; Disable interrupts.
; Clear T1IC int. priority level and int. request bit.
;
I
; Enable interrupts.
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