參數(shù)資料
型號： M30100
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述： 單片16位CMOS微機(jī)
文件頁數(shù)： 66/164頁
文件大?。?/td> 3302K
代理商： M30100
deveopment
Tentative Specifications REV.E1
Timer X
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
65
(2) Pulse output mode
In this mode, the timer counts an internally generated count source, and outputs from the CNTR0 pin
a pulse whose polarity is inverted each time the timer underflows. (See Table 1.14.4) Figure 1.14.7
shows Timer X mode register in pulse output mode.
Item
Specification
Count source
Count operation
f
1
, f
8
, f
32
, f
C32
Down count
When the timer underflows, it reloads the reload register contents before continuing counting
1/(n+1)/(m+1) n : Set value of Prescaler X, m: Set value of Timer X
Count start flag is set (=1)
Count start flag is reset (=0)
Interrupt request generation timing
When Timer X underflows [Timer X interruption]
Rising (R0EDG=0) or falling (R0EDG=1) of CNTR0 output [CNTR0 interruption] (Note)
CNTR0 pin function
Pulse output
TX
OUT
pin function
Programmable I/O port or pulse output (Inverted waveform of the pulse output from the
CNTR0 pin)
Read from timer
Count value can be read out by reading Timer X register.
Same applies to Prescaler X register.
Write to timer
When a value is written to Timer X register, it is written to both reload register and counter.
Same applies to Prescaler X register.
Select function
Pulse output function
Each time the timer underflows, the TX
OUT
pin’s polarity is reversed
CNTR0 polarity switching function
The polarity level at starting of pulse output can be selected to be "High" or "Low" with software.
Note: When setting the timer X mode register to pulse output mode, the CNTR0 interrupt request bit becomes "1".
Thus, when using an CNTR0 interrupt, the CNTR0 interrupt request bit must be set to "0" after setting the timer
X mode register.
Divide ratio
Count start condition
Count stop condition
Table 1.14.4. Specifications of pulse output mode
Timer X mode register
Symbol
TXMR
Address
008B
16
When reset
00000000
2
Bit name
Function
Bit symbol
W
R
b7
b6 b5
b4
b3
b2
b1 b0
0
b1 b0
TXMOD2
TXS
TXMOD1
R0EDG
TXMOD0
TXOCNT
CNTR0 polarity
switching bit
Operation mode
select bit 0, 1
Note 1: In the pulse output mode, the direction register of port P1
7
must be set to input.
Note 2: Output is set regardless of the setting of the direction register of port P3
0
.
Note 3: This bit should rewrite with inhibiting the CNTR0 interrupt.
AA
AA
AA
AA
AA
AA
AA
AA
0: Output starts at "H" (Interrupt at rising edge)
1: Output starts at "L" (Interrupt at falling edge)
Timer X count
start flag
P3
0
/TX
OUT
select bit
0 : Stops counting
1 : Starts counting
0 : Port P3
0
1 : TX
OUT
output
0 : Set to "0" in pulse output mode
(Note 1)
(Note 2)
0
1
(Note 3)
AA
Invalid in pulse output mode.
When write, set "0". When read, this contents is indeteminate.
TXEDG
TXUND
Invalid in pulse output mode.
When write, set "0". When read, this contents is indeteminate.
Figure 1.14.7. Timer X mode register in pulse output mode
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