參數(shù)資料
型號(hào)： M37641M8-XXXHP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 15/149頁
文件大?。?/td> 1997K
代理商： M37641M8-XXXHP
15
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7641 Group
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
Table 6 List of I/O port function
Name
Port P0
Port P1
Port P2
Input/Output
Input/Output,
individual bits
I/O format
CMOS input level
CMOS 3-state output
Non-port function
Lower address
output
Higher address
output
Data bus I/O
Related SFRs
CPU mode register A
Port control register
Ref. No.
(1)
P0
0
/AB
0
–
P0
7
/AB
7
P1
0
/AB
8
–
P1
7
/AB
15
P2
0
/DB
0
–
P2
7
/DB
7
P6
0
/DQ
0
–
P6
7
/DQ
7
Pin
(2)
CPU mode register A
Port control register
Port P2 pull-up control
register
CPU mode register A
CPU mode register B
Port control register
CPU mode register A
CPU mode register B
Port control register
Timer X mode register
Timer Y mode register
Interrupt polarity select register
CPU mode register A
Port control register
Clock control register
Timer 123 mode register
Data bus buffer control
register 0
Port control register
Control signal I/O
CMOS input level/VIHL
input level
CMOS 3-state output
Port P3
(1)
(3)
(4)
(5)
CMOS input level
CMOS 3-state output
P3
0
/RDY
–
P3
7
/RD
P4
0
/EDMA,
Port P4
P4
1
/INT
0
,
P4
2
/INT
1
,
P4
3
/CNTR
0
,
P4
4
/CNTR
1
Control signal I/O
External interrupt
P5
0
/X
CIN
,
P5
1
/T
OUT
/
X
COUT
CMOS input level
CMOS 3-state output
(6)
(7)
Timer 1, Timer 2
output pin
Sub-clock generat-
ing input pin
P5
2
/OBF
0
,
P5
3
/IBF
0
,
P5
4
/S
0
,
P5
5
/A
0
,
P5
6
/R(E),
P5
7
/W(R/W)
Port P5
CMOS input level
CMOS 3-state output
CMOS input level/TTL
input level in Master
CPU bus inferface
function
(8)
(9)
(10)
CMOS input level/TTL
input level
CMOS 3-state output
CMOS input level
CMOS 3-state output
CMOS input level
CMOS 3-state output
CMOS input level/TTL
input level in Master
CPU bus inferface
function
CMOS input level
CMOS 3-state output
(11)
Data bus buffer control
register 0
Port control register
USB control register
Port control register
Data bus buffer control
register 1
Port control register
CPU mode register B
P7
0
/SOF,
Port P6
Port P7
P7
1
/HOLD,
P7
2
/S
1
,
P7
3
/IBF
1
/
HLDA,
P7
4
/OBF
1
(12)
(13)
(14)
(15)
(16)
Master CPU bus
interface I/O pin
Master CPU bus
interface I/O pin
USB function output
pin
Control signal I/O
Master CPU bus
interface I/O pin
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
UART1, 2 control registers
Serial I/O control register 1
Serial I/O control register 2
Port control register
Serial I/O I/O pin
UART2 I/O pin
UART1 I/O pin
P8
0
/UTXD
2
/
SRDY,
P8
1
/URXD
2
/
SCLK,
P8
2
/CTS
2
/
SRXD,
P8
3
/RTS
2
/
STXD,
P8
4
/UTXD
1
,
P8
5
/URXD
1
,
P8
6
/CTS
1
,
P8
7
/RTS
1
Port P8
Notes 1
: For details of the ports functions in modes other than single-chip mode, and how to use double-function ports as function I/O ports, refer to the applicable
sections.
2
: Make sure that the input level at each pin is either 0 V or V
CC
during execution of the STP instruction.
When an input level is at an intermediate potential, a rush current will flow from V
CC
to V
SS
through the input-stage gate.
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