參數(shù)資料
型號： M37641M8-XXXHP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機
文件頁數(shù)： 24/149頁
文件大小： 1997K
代理商： M37641M8-XXXHP
24
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
TIMERS
The 7641 group has five timers: timer X, timer Y, timer 1, timer 2,
and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,
timer 2, and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “00
16
”
or “0000
16
”, an underflow occurs at the next count pulse and the
corresponding timer latch is reloaded into the timer and the count
is continued. When a timer underflows, the interrupt request bit
corresponding to that timer is set to “1”.
Read and write operation on 16-bit timer must be performed for
both high and low-order bytes. When reading a 16-bit timer, read
the high-order byte first. When writing to a 16-bit timer, write the
low-order byte first. The 16-bit timer cannot perform the correct
operation when reading during the write operation, or when writing
during the read operation.
Fig. 19 Timer block diagram
P4
4
/CNTR
1
P4
3
/CNTR
0
Q
T
SCSGCLK
Q
T
S
P5
1
/T
OUT
/X
COUT
Timer X (low) (8)
Timer X (high) (8)
Timer X (low) latch (8)
Timer X (high) latch (8)
φ
/ 8
φ
/ 16
φ
/ 32
φ
/ 64
Timer X internal clock
select bit
Timer X count source
select bits
Timer X
operating
mode bits
“
00
”
“
01
”
Timer X count
stop bit
“
11
”
“
10
”
“
0
”
“
1
”
P5
4
direction register
CNTR
0
active edge
switch bit
CNTR
0
active edge
switch bit
P4
3
latch
Pulse output mode
Pulse output mode
Q
“
0
”
“
1
”
Falling edge detection
Rising edge detection
Pulse width HL continuously
measurement mode
Pulse width HL
continuously measurement,
Period measurement modes
Timer X interrupt
request
CNTR
0
interrupt
request
Timer X write control bit
φ
/ 8
φ
/ 16
φ
/ 32
φ
/ 64
“
00
”
“
01
”
“
11
”
CNTR
1
active
edge s“
“
10
”
Timer Y
operating mode
bits
0
”
“
1
”
Timer mode,
TY
OUT
output enabled
Timer Y count
stop bit
Timer Y (low) latch (8)
Timer Y (low) (8)
Timer Y (high) (8)
Timer Y (low) high (8)
Timer Y write
control bit
Q
Timer mode,
TY
OUT
output ena“
CNTR
1
active
edge switch bit
0
”
“
1
”
Timer Y
operating mode
bits
“
00
”
“
01
”
“
10
”
“
11
”
Timer Y interrupt
request
CNTR
1
interrupt
request
Timer 1 interrupt
request
Timer 2 interrupt
request
Timer 3 interrupt
request
Timer 1 count
source select bit
“
0
”
φ
/ 8
f(X
CIN
) / 2
“
1
”
Timer 1 count
stop bit
Timer 1 latch (8)
Timer 1 (8)
Timers 1, 2 write control
bit
Timers 1, 2 write control
bit
“
0
”
“
1
”
Timer 2 count
source select bit
Timer 2 latch (8)
Timer 2 (8)
φ
T
OUT
output control bit
“
0
”
“
1
”
T
OUT
output active
edge switch bit
T
OUT
output
control bit
T
OUT
source
select bit
Q
T
Q
Q
T
Q
T
OUT
output control bit
“
0
”
“
1
”
T
OUT
output active
edge switch bit
φ
/ 8
Timer 3 count
source select bit
Timer 3 latch (8)
Timer 3 (8)
“
0
”
“
1
”
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