參數(shù)資料
型號： M37641M8-XXXHP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機
文件頁數(shù)： 60/149頁
文件大?。?/td> 1997K
代理商： M37641M8-XXXHP
60
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
Fig. 55 Structure of master CPU bus interface related registers
Data bus buffer status register 0 (address 0049
16
)
DBBS0
O
u
0
1
p
0
1
s
T
t
:
:
u
:
:
e
h
f
h
h
s
e
T
p
B
B
t
B
B
r
i
l
a
i
e
r
h
u
u
u
b
u
u
d
s
g
s
I
d
i
s
t
f
f
u
f
f
f
f
e
f
l
f
B
e
f
b
f
e
f
e
f
e
e
f
a
(
A
00
)
l
a
g
F
0
f
i
n
l
a
g
u
r
r
f
r
r
i
n
g
f
f
e
f
r
e
f
a
c
e
r
f
p
u
t
l
y
l
f
l
a
g
(
O
B
F
0
)
m
u
f
m
u
b
a
l
u
l
I
n
e
l
p
l
t
f
y
l
a
g
(
I
B
F
0
)
l
l
U
l
e
n
f
b
l
a
e
g
d
(
e
U
2
)
f
i
n
e
d
b
y
u
s
e
r
f
r
e
e
l
y
.
A
0
T
t
i
n
l
a
b
c
d
g
l
e
a
n
i
c
a
s
f
l
b
t
a
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s
g
s
e
d
t
(
e
t
.
U
4
–
f
i
n
h
e
c
o
n
d
i
t
i
o
n
o
f
A
0
s
t
a
t
u
s
w
h
e
n
f
i
U
a
U
7
)
e
d
b
y
u
s
e
r
f
r
e
e
l
y
.
b
0
b
7
Data bus buffer control register 0 (address 004A
16
)
DBBC0
O
B
0
1
F
0
0
:
1
:
B
F
0
0
F
0
:
P
:
P
o
5
2
5
2
o
u
P
5
3
P
5
3
i
n
:
O
c
o
1
:
O
u
t
p
u
0
:
E
1
:
D
n
p
u
t
0
:
E
1
:
D
R
e
s
e
M
a
s
t
0
:
1
:
u
t
f
f
p
u
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f
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f
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r
r
u
m
u
b
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a
b
s
a
b
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f
n
a
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s
a
r
v
e
e
r
C
P
5
4
P
5
4
b
u
s
i
n
t
e
:
R
D
1
:
R
/
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n
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n
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r
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a
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a
,
W
W
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0
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b
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(
t
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p
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.
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p
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n
.
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B
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B
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A
0
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I
/
o
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.
F
0
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p
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n
.
I
t
e
c
m
c
c
t
n
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d
a
=
o
t
e
t
m
r
r
a
“
1
w
”
)
m
u
p
r
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t
e
(
A
0
=
“
0
”
)
o
r
n
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a
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(
A
0
i
t
=
“
1
”
)
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s
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r
r
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b
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b
i
t
b
5
7
,
5
7
,
r
f
a
t
s
e
(
“
u
0
s
”
P
P
c
e
y
p
e
p
b
u
a
i
n
6
0
6
0
f
u
e
s
a
r
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t
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r
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t
t
c
l
t
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a
f
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P
P
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/
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6
7
6
7
n
t
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f
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a
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)
b
c
c
.
l
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m
/
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r
r
t
s
C
.
P
U
n
e
B
u
0
s
a
b
u
s
t
b
0
b7
Data bus buffer status register 1 (address 004D
16
)
DBBS1
O
u
0
1
p
0
1
s
T
t
:
:
u
:
:
e
h
f
h
h
s
e
T
p
B
B
t
B
B
r
i
l
a
i
e
r
h
u
u
u
b
u
u
d
s
g
s
I
d
i
s
t
f
f
u
f
f
f
f
e
f
l
f
B
e
f
b
f
e
f
e
f
e
e
f
a
(
A
01
)
l
a
g
F
1
f
i
n
l
a
g
u
r
r
f
r
r
i
n
g
f
f
e
f
r
e
f
a
c
e
r
f
p
u
t
l
y
l
f
l
a
g
(
O
B
F
1
)
m
u
f
m
u
b
a
l
u
l
I
n
e
l
p
l
t
f
y
l
a
g
(
I
B
F
1
)
l
l
U
l
e
n
f
b
l
a
e
g
d
(
e
U
2
)
f
i
n
e
d
b
y
u
s
e
r
f
r
e
e
l
y
.
A
0
T
t
i
n
l
a
b
c
d
g
l
e
a
n
i
c
a
s
f
l
b
t
a
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e
s
g
s
e
d
t
(
e
t
.
U
4
–
f
i
n
h
e
c
o
n
d
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t
i
o
n
o
f
A
0
s
t
a
t
u
s
w
h
e
n
f
i
U
a
U
7
)
e
d
b
y
u
s
e
r
f
r
e
e
l
y
.
b
0
b
7
O
B
0
1
F
1
0
:
1
:
B
F
1
0
F
1
:
P
:
P
o
7
4
7
4
o
u
P
7
3
P
7
3
i
n
:
O
c
o
1
:
O
u
t
p
u
0
:
E
1
:
D
n
p
u
t
0
:
E
1
:
D
R
e
s
e
D
a
t
a
0
:
u
t
f
f
p
u
u
u
f
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r
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m
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a
b
s
a
b
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f
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a
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s
a
r
v
e
b
u
S
i
n
(
P
7
2
:
D
o
(
P
7
2
u
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a
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f
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b
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b
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c
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d
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d
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1
d
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1
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p
b
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(
t
y
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/
I
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1
p
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.
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t
p
u
t
p
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n
.
I
B
t
p
p
I
B
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o
A
0
t
o
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o
r
t
I
/
o
O
u
t
p
p
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u
n
.
F
1
t
p
i
n
.
I
t
e
c
m
c
c
t
n
i
c
d
a
=
o
t
e
t
m
r
r
a
“
1
w
”
)
m
u
p
r
i
t
e
(
A
0
=
“
0
”
)
o
r
n
c
a
t
n
d
d
i
w
a
r
i
l
t
e
e
b
(
A
0
i
t
=
“
1
”
)
O
s
b
I
f
u
l
l
i
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
b
i
t
f
(
e
a
c
d
n
c
“
0
r
t
a
t
i
a
t
i
”
f
u
b
o
n
t
a
o
n
a
n
u
s
b
s
t
c
s
a
u
a
r
e
t
i
s
s
s
a
o
b
b
d
n
u
I
/
u
S
1
/
s
f
f
O
f
w
e
e
f
e
i
r
l
i
e
m
p
o
r
n
p
t
e
c
)
t
o
r
t
m
u
f
d
n
b
d
.
)
o
t
i
t
r
e
1
u
d
p
e
i
n
.
)
b
0
b7
Data bus buffer control register 1 (address 004E
16
)
DBBC1
0
0 0
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