參數(shù)資料
型號： M37641M8-XXXHP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機
文件頁數(shù)： 20/149頁
文件大?。?/td> 1997K
代理商： M37641M8-XXXHP
20
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7641 Group
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
INTERRUPTS
There are twenty-four interrupt sources: five externals, eighteen
internals, and one software.
Interrupt Control
Each interrupt except the BRK instruction interrupt has both an Inter-
rupt Request Bit and an Interrupt Enable Bit, and is controlled by the
Interrupt Disable Flag (I). An interrupt occurs if the corresponding
Interrupt Request and Enable Bits are
“
1
”
and the Interrupt Disable
Flag is
“
0
”
.
Interrupt Enable Bits can be set or cleared by software. Interrupt Re-
quest Bits can be cleared by software, but cannot be set by software.
Additionally, an active edge of INT
1
and INT
2
can be selected by
using the interrupt edge select register (address 0011
16
); an active
edge of CNTR
0
can be done by using the timer X mode register
(address 0027
16
); an active edge of CNTR
1
can be done by using
the timer Y mode register (address 0028
16
).
The BRK instruction interrupt and reset cannot be disabled with any
flag or bit. The I Flag disables all interrupts except the BRK instruc-
tion interrupt and reset. If several interrupts requests occur at the
same time, the interrupt with the highest priority is accepted first.
Interrupt Operation
When an interrupt request occurs, the following operations are auto-
matically performed:
1.The processing being executed is stopped.
2.The contents of the program counter and processor status reg-
ister are automatically pushed onto the stack.
3.The Interrupt Disable Flag is set and the corresponding in-
terrupt request bit is cleared.
4.The interrupt jump destination address is read from the vector
table into the program counter.
I
Notes
When setting the followings, the interrupt request bit may be set to
“
1
”
.
When setting external interrupt active edge
Related register: Interrupt polarity select register (address 0011
16
)
Timer X mode register (address 0027
16
)
Timer Y mode register (address 0028
16
)
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
Set the corresponding Interrupt Enable Bit to
“
0
”
(disabled).
Set the Interrupt Edge Select Bit (Active Edge Switch Bit).
Set the corresponding Interrupt Request Bit to
“
0
”
after 1 or more
instructions have been executed.
Set the corresponding Interrupt Enable Bit to
“
1
”
(enabled).
Fig. 16 Interrupt control
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(
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)
BRK instruction
Reset
Interrupt request
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