參數(shù)資料
型號(hào)： M37641M8-XXXHP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 90/149頁
文件大小： 1997K
代理商： M37641M8-XXXHP
90
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7641 Group
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
Table 19 Electrical characteristics (1)
(Vcc = 3.0 to 3.6 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted)
Electrical Characteristics
In Vcc = 3 V
I
OH
= –1 mA
“H” output voltage
P0
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7,
P3
0
–P3
7,
P4
0
–P4
4,
P5
0
–P5
7,
P6
0
–P6
7,
P7
0
–P7
4,
P8
0
–P8
7
“H” output voltage
USB D+, USB D-
Limits
Typ.
V
Parameter
Min.
V
CC
–1.0
Max.
Symbol
Unit
Test conditions
V
OH
V
OH
USB+, and USB- pins
pull-down via a resistor
of 15 k
±
5
%
USB+ pin pull-up to Ext.
Cap. pin via a resistor of
1.5 k
±
5
%
I
OL
= 1 mA
V
OL
“L” output voltage
P0
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7,
P3
0
–P3
7,
P4
0
–P4
4,
P5
0
–P5
7,
P6
0
–P6
7,
P7
0
–P7
4,
P8
0
–P8
7
“L” output voltage
USB D+, USB D-
USB+, and USB- pins
pull-down via a resistor
of 15 k
±
5
%
USB+ pin pull-up to Ext.
Cap. pin via a resistor of
1.5 k
±
5
%
V
T+
–V
T-
Hysteresis
CNTR
0
, CNTR
1
, INT
0
, INT
1
, RDY, HOLD,
P2
0
–P2
7
Hysteresis
URXD1, URXD2 (SCLK), CTS
2
(SRXD),
SRDY, CTS
1
Hysteresis
RESET
“H” input current
P0
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7,
P3
0
–P3
7,
P4
0
–P4
4,
P5
0
–P5
7,
P6
0
–P6
7,
P7
0
–P7
4,
P8
0
–P8
7
“H” input current
RESET, CNV
SS
“H” input current
X
IN
“H” input current
X
CIN
“L” input current
P0
0
–P0
7
, P1
0
–P1
7
, P3
0
–P3
7,
P4
0
–P4
4,
P5
0
–P5
7,
P6
0
–P6
7,
P7
0
–P7
4,
P8
0
–P8
7
“L” input current
RESET
“L” input current
CNV
SS
“L” input current
X
IN
“L” input current
X
CIN
“L” input current
P2
0
–P2
7
V
T+
–V
T-
V
T+
–V
T-
I
IH
I
IH
I
IH
I
IH
I
IL
I
IL
I
IL
I
IL
I
IL
I
IL
V
I
= V
CC
V
I
= V
SS
V
I
= V
SS
Pull-ups “off”
V
CC
= 3.0 V, V
I
= V
SS
Pull-ups “on”
When clock is stopped
2.8
–10
2.0
0.3
0.3
0.3
9.0
–9.0
–20
3.6
1.0
0.3
5.0
5.0
20
5.0
–5.0
–5.0
–20
–20
–5.0
–5.0
V
V
V
V
V
V
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
V
OL
–50
V
V
RAM
0
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