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參數(shù)資料
| 型號： | M37641M8-XXXHP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 45/149頁 |
| 文件大?。?/td> | 1997K |
| 代理商： | M37641M8-XXXHP |
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45
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
USB Reception
Endpoint 0 to Endpoint 4 have OUT (receive) FIFOs individually.
Each endpoint
’
s FIFO is configured in following way:
Endpoint 0: 16-byte
Endpoint 1: Mode 0: 800-byte
Mode 1: 1024-byte
Mode 2: 2048-byte
Mode 3: 0-byte
Mode 4: 1280-byte
Mode 5: 1168-byte
Endpoint 2: Mode 0: 32-byte
Mode 1: 128-byte
Endpoint 3: 16-byte
Endpoint 4: 16-byte
When Endpoint 1 or Endpoint 2 is used for data receive, the OUT
FIFO size can be selected. Endpoint 1 and Endpoint 2 have pro-
grammable IN-FIFOs size; 6 modes for Endpoint 1, and 2 modes
for Endpoint 2. Each mode can be selected by the USB endpoint
FIFO mode selection register (address 005F
16
).
Data transmitted from the host-PC is stored in Endpoint x FIFO
(0060
16
to 0064
16
). Every time the data is stored in the FIFO, the
internal OUT FIFO write pointer is increased by 1. When one com-
plete data packet is stored, the OUT_PKT_RDY flag is set to
“
1
”
and the number of received data packets is stored in USB End-
point x OUT write count registers (Low and High). When the
AUTO_CLR bit is
“
1
”
and the received data is read out from the
OUT FIFO, the OUT_PKT_RDY flag is cleared to
“
0
”
. When the
AUTO_CLR bit is
“
1
”
, the OUT_PKT_RDY flag will not be cleared
automatically by the FIFO read; it must be cleared by software.
(The AUTO-CLR bit function is not applicable in Endpoint 0.)
When MAXP size
≤
(a half of OUT FIFO size), the OUT_FIFO can
receive 2 packets (double buffer). At this time, the OUT_ FIFO sta-
tus can be checked by the OUT_PKT_RDY flag. When the FIFO
holds two packets and one packet is read from the FIFO, the
OUT_PKT_RDY flag is not cleared even if it is set to
“
0
”
. (The flag
returns from
“
0
”
to
“
1
”
in one
φ
cycle after the read-out). During
double buffer mode, the USB Endpoint x OUT write count regis-
ters (Low and High) holds the number of previously received
packets. This count register is updated after reading out one of
packets in the OUT FIFO and clearing the OUT_PKT_RDY flag to
“
0
”
.
When Endpoint 1 OUT is used and its MAXP size
≤
(one third of
OUT FIFO size), this can be used as triple buffer. However, before
the third EOF packet has been received, be sure to read the first
packet data and clear the OUT_PKT_RDY flag.
If the third packet data has been received before the first packet
data is read, an overrun error occurs and the third packet data is
destroyed.
TOGGLE Initialization
In order to initialize the data toggle sequence bit of the endpoint,
in other words, resetting the next data packet to DATA0; set the
ISO/TOGGLE_INT bit to
“
1
”
and then clear back to
“
0
”
.
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