參數(shù)資料
型號: M37920FCCHP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 114/158頁
文件大?。?/td> 1261K
代理商: M37920FCCHP
59
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
CLOCK SYNCHRONOUS SERIAL COMMUNI-
CATION
A case where communication is performed between two clock syn-
chronous serial I/O ports as shown in Figure 55 will be described.
(The transmission side will be denoted by subscript j and the receiv-
ing side will be denoted by subscript k.)
Bit 0 of the UARTj transmit/receive mode register and UARTk trans-
mit/receive mode register must be set to “1” and bits 1 and 2 must be
“0”. The length of the transmission data is fixed at 8 bits.
Bit 3 of the UARTj transmit/receive mode register of the clock send-
ing side is cleared to “0” to select the internal clock. Bit 3 of the
UARTk transmit/receive mode register of the clock receiving side is
set to “1” to select the external clock. Bits 4, 5 and 6 are ignored in
clock synchronous mode. Bit 7 must always be “0”.
The clock source is selected by bit 0 (CS0) and bit 1 (CS1) of the
clock-sending-side UARTj transmit/receive control register 0. As
shown in Figure 50, the selected clock is divided by (n + 1), then by
2, is passed through a transmission control circuit, and is output as
transmission clock CLKj. Therefore, when the selected clock is fi,
Bit Rate = fi/ {(n + 1)
× 2}
On the clock receiving side, the CS0 and CS1 bits of the UARTk
transmit/receive control register 0 are ignored because an external
clock is selected.
UART0 is equipped with the CTS and RTS functions.
UART1 is not equipped with the CTS/RTS function.
Bit 4 of the UART0 transmit/receive control register 0 is used to de-
termine whether to use CTS0 or RTS0 signal. Bit 4 must be “0” when
CTS0 or RTS0 signal is used. Bit 4 must be “1” when CTS0 and RTS0
signals are not used. When CTS0 and RTS0 signals are not used,
CTS0/RTS0 pin can be used as a normal port pin.
When using this pin as pin CTS0/RTS0, :
If bit 2 of the UART0 transmit/receive control register 0 is cleared to
“0”, CTS0 input is selected.
If bit 2 is set to “1”, RTS0 output is selected.
Figure 56 shows the bit configuration of the CTS/RTS separate se-
lect register. By using bit 0 of the CTS/RTS separate select register
(CTS/RTS separate select bit), the function of the CTS0/RTS0 pin
can be separated into two functions. When bit 0 = “1”, the above
separation is performed. When bit 0 = “0”, no separation is per-
formed. When the CTS0/RTS0 pin is separated, RTS0 function is
selected. When the CTS0/CLK1 pin is separated, CTS0 function is
selected.
The following describes the case where the CTS and RTS signals
are used. When the CTS and RTS signals are not used, however,
the CTS input is not necessary, and there is no RTS output.
Since UART1 is not equipped with the CTS/RTS function, UART1 is
regarded as the case where the CTS and RTS signals are not used.
Fig. 55 Clock synchronous serial communication
UARTj transmit register
TxDj
RxDj
CLKj
CTSj
UARTj transmit buffer register
UARTj receive buffer register
UARTj receive register
UARTj Transmit/Receive mode register
UARTj Transmit/Receive control
register 0
UARTj Transmit/Receive control
register 1
00
0
TX
EPTY
CS1
CS0
RE
RI
OER
FER
PER
CPL
SUM
TI
TE
0
UARTk transmit register
UARTk transmit buffer register
UARTk receive buffer register
UARTk receive register
UARTk Transmit/Receive mode register
UARTk Transmit/Receive control
register 0
UARTk Transmit/Receive control
register 1
01
1
0
1
TX
EPTY
MSB
/LSB
RE
RI
OER
FER
PER
SUM
TI
TE
0
1
TxDk
RxDk
CLKk
RTSk
MSB
/LSB
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