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參數(shù)資料
| 型號(hào)： | M37920FCCHP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁(yè)數(shù)： | 128/158頁(yè) |
| 文件大?。?/td> | 1261K |
| 代理商： | M37920FCCHP |
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71
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
tween an external I/O and the external memory, this method allows
the memory to be read at the same time the data is written to the
external I/O, and vice versa, resulting in fast data transfer. Bit 0 of the
DMAi mode register H determines whether the 1-bus cycle transfer
is to be made from the external memory to the external I/O or from
the external I/O to the external memory. When the bit is “1”, the data
transfer is made from the external I/O to the external memory.
Figure 71 shows an connection example with external memories and
external I/Os in 1-bus cycle transfer (the external data bus width = 16
bits and “1 transfer unit” = 16 bits).
For the transfer from the external memory to external I/O, the exter-
nal-memory-side address (transfer source address) is output to the
address bus, pin RD goes to “L”, and the read operation will be per-
formed.
This ensures that the data is read out from the external memory. At
the same time, pin DMAACKi corresponding to the operating DMAi
channel (i = 0 to 2) goes to “L”, the external I/O is selected, and the
data read from the external memory is directly fetched at the rising of
signal RD. In this manner, data is transferred from external memory
to external I/O in 1 bus cycle.
For the transfer from the external I/O to the external memory, the
data is read out from the external I/O, selected by the acknowledge
signal from pin DMAACKi, to the data bus. At the same time, the ex-
ternal-memory-side address (transfer destination address) is output
to the address bus, pin BLW (write signal for even-numbered ad-
dresses) and pin BHW (write signal for odd-numbered addresses)
go to “L”, and the write operation to the external memory is per-
formed.
The 1-bus cycle transfer cannot perform operations for a read from
or a write to the internal memory. In order to perform the transfer from
the internal memory to the external I/O or from the external I/O to the
internal memory, be sure to select the 2-bus cycle transfer method.
Data transfer method
Two different data transfer methods are available: 2-bus cycle trans-
fer, effective for memory-to-memory data transfer, and 1-bus cycle
transfer, effective for memory-to-I/O or I/O-to-memory data transfer.
Both methods are described in detail below.
(1) 2-bus cycle transfer
When bit 1 of the DMAi mode register L, as shown in Figure 69, is
cleared to “0”, the 2-bus cycle transfer method is selected. This
method makes data to be transferred by the “1 transfer unit”, by us-
ing 1 read bus cycle and 1 write bus cycle. The “1 transfer unit” re-
fers to the number of bits which can be transferred in 1 DMA transfer
operation, and it is determined by bit 0 of the DMAi mode register L.
When bit 0 is cleared to “0”, “1 transfer unit” consists of 16 bits (2
bytes); when “1”, “1 transfer unit” consists of 8 bits (1 byte).
In the 2-bus cycle transfer, be sure to clear bit 0 of the DMAi mode
register H to “0”.
Figure 70 shows an connection example with external memories in
2-bus cycle transfer. In the read cycle, the transfer source address is
output to the address bus, and the data at this address is read out by
the “1 transfer unit” and then stored into the BIU’s data buffer. When
16-bit data is read out from an odd-numbered address or when 16-
bit data is read out with the external data bus width = 8 bits, the mi-
crocomputer will enter the write cycle after the above 16-bit data is
stored into the BIU’s data buffer in 2 accesses.
In the write cycle, the transfer destination address is output to the
address bus, and the data which has been stored in the BIU’s data
buffer is written to the transfer destination address. When 16-bit data
is read out from an odd-numbered address or when 16-bit data is
read out with the external data bus width = 8 bits, the microcomputer
will preforms the write operation in 2 accesses.
(2) 1-bus cycle transfer
When bit 1 of the DMAi mode register L is set to “1”, the 1-bus cycle
transfer method is selected. When data transfer is to be made be-
Fig. 65 Block diagram of DMA controller
Internal address bus
: Internal bus
: DMA controller’s bus
Internal address bus
Decrementer
Incrementer/Decrementer
Source address register 0 (SAR0)
Destination address register 0 (DAR0)
Source address register 1 (SAR1)
Destination address register 1 (DAR1)
Source address register 2 (SAR2)
Destination address register 2 (DAR2)
Destination address register 3 (DAR3)
Source address register 3 (SAR3)
Transfer counter register 0 (TCR0)
Transfer counter register 1 (TCR1)
Transfer counter register 2 (TCR2)
Transfer counter register 3 (TCR3)
Bus
Interface
Unit
(BIU)
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PDF描述 |
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| M38039MFL-XXXWG | 8-BIT, MROM, 16.8 MHz, MICROCONTROLLER, PBGA64 |
| M38039FFLSP | 8-BIT, FLASH, 16.8 MHz, MICROCONTROLLER, PDIP64 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37920FGCGP | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37920FGCHP | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37920S4CGP | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:16 BIT CMOS MICROCOMPUTER |
| M37P75C4P3 | 功能描述:汽車(chē)連接器 Pin Contact RoHS:否 制造商:Amphenol SINE Systems 產(chǎn)品:Contacts 系列:ATP 位置數(shù)量: 型式:Female 安裝風(fēng)格: 端接類(lèi)型: 觸點(diǎn)電鍍:Nickel |
| M37S07K4F3 | 功能描述:汽車(chē)連接器 Sckt Contact RoHS:否 制造商:Amphenol SINE Systems 產(chǎn)品:Contacts 系列:ATP 位置數(shù)量: 型式:Female 安裝風(fēng)格: 端接類(lèi)型: 觸點(diǎn)電鍍:Nickel |
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