- 您現(xiàn)在的位置：買賣IC網 > PDF目錄69015 > M37920FCCHP 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100 PDF資料下載
參數(shù)資料
| 型號： | M37920FCCHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 136/158頁 |
| 文件大?。?/td> | 1261K |
| 代理商： | M37920FCCHP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁當前第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁
79
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
Fig. 74 Example of cycle steal transfer
DMAREQ0
DMA0 request bit
DMA0 enable bit
(CPU) DMA1
(CPU)
The above example applies on the following conditions :
DMA request sources of DMA0 and DMA1: external source
Channel priority : fixed (channel 0 > channel 1)
DMA0
DMA1 DMA0
DMA1
DMAREQ1
DMA1 request bit
DMA1 enable bit
DRAM refresh request
Bus user
DRAM
refresh
(2) Cycle steal transfer mode
When bit 2 of the DMAi mode register L is set to “1”, the cycle steal
transfer mode is selected. In the cycle steal transfer mode, be sure
to select the edge sense mode.
When a DMA request occurs in the cycle steal transfer mode, the
corresponding DMA request bit is set to “1” as in the burst transfer
mode. When the DMA request from the channel is accepted, DMA
transfer starts. However, the DMA request bit is automatically
cleared to “0” at the start of the first DMA transfer cycle. Therefore, if
there is no DMA request from any channel when 1-transfer-unit data
has been transferred, the DMA controller returns the right to use bus
to the CPU. If there is a DMA request from a channel, the DMA con-
troller continues to use the bus and initiates DMA transfer for the
channel. In the cycle steal transfer mode, the priorities of the chan-
nels are detected at all times to assure that the DMA request from a
channel having the highest priority is accepted to initiate the DMA
transfer execution. The DMA request bit is cleared to “0”, at each
time when 1-transfer-unit data has been transferred. At this time,
however, the DMA enable bit will not be cleared to “0” although the
DMA request bit is cleared to “0” at each transfer of 1 transfer unit.
Therefore, when the DMA request bit is set to “1” next, transfer is re-
sumed at the point of interruption. When the transfer counter
register’s value is “0” in the single transfer, or when both of the trans-
fer counter register’s value and transfer block counter’s value are “0”
in the array chain transfer, the DMA enable bit will be cleared to ”0”
to terminate the whole DMA transfer operation.
Figure 74 shows an example of cycle steal transfer. When pin
DMAREQi’s input level changes from “H” to “L”, the DMA1 request
bit will be set to “1” and the DMA controller will acquire the right to
use bus and initiate DMA transfer. The DMA1 request bit is cleared
to “0” when the channel 1 transfer cycle starts. Therefore, if there is
no DMA transfer request from the other channels, the DMA control-
ler returns the right to use bus to the CPU at the end of 1 transfer
cycle. In the example shown in Figure 74, however, DMA0 transfer
cycle execution continues because the channel 0’s request bit is set
to “1”. When the DMA0 transfer cycle is terminated, the DMA re-
quest bits of all channels are cleared to “0” so that the DMA control-
ler returns the right to use bus to the CPU. When the DMA1 request
bit is set to “1”, only one cycle of transfer operation is performed.
Even if the DMA1 request bit is cleared to “0” at this time, the DMA1
request bit is set to “1” again to perform continuous transfer, as long
as pin DMAREQi’s input level goes “L” before the end of the next
transfer cycle. In the cycle steal transfer, the priorities of individual
channels are detected at the end of each transfer cycle. Therefore, if
the request is issued from channel 0, which has a higher priority than
channel 1, channel 0 transfer is executed first. Furthermore, if a re-
quest to use bus which has a higher priority (for example, a refresh
request from the DRAM controller) is generated, this request takes
the precedence.
相關PDF資料 |
PDF描述 |
|---|---|
| M37920FCCGP | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100 |
| M38039MFL-XXXWG | 8-BIT, MROM, 16.8 MHz, MICROCONTROLLER, PBGA64 |
| M38039FFLSP | 8-BIT, FLASH, 16.8 MHz, MICROCONTROLLER, PDIP64 |
| M38039FFLKP | 8-BIT, FLASH, 16.8 MHz, MICROCONTROLLER, PQFP64 |
| M38049FFLWG | 8-BIT, FLASH, 16.8 MHz, MICROCONTROLLER, PBGA64 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M37920FGCGP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37920FGCHP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37920S4CGP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16 BIT CMOS MICROCOMPUTER |
| M37P75C4P3 | 功能描述:汽車連接器 Pin Contact RoHS:否 制造商:Amphenol SINE Systems 產品:Contacts 系列:ATP 位置數(shù)量: 型式:Female 安裝風格: 端接類型: 觸點電鍍:Nickel |
| M37S07K4F3 | 功能描述:汽車連接器 Sckt Contact RoHS:否 制造商:Amphenol SINE Systems 產品:Contacts 系列:ATP 位置數(shù)量: 型式:Female 安裝風格: 端接類型: 觸點電鍍:Nickel |
發(fā)布緊急采購，3分鐘左右您將得到回復。