
27
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
Selection of processor mode
Figures 11, 12 show the bit configurations of the processor mode
registers 0, 1.
Any of the three processor modes (single-chip mode, memory ex-
pansion mode, microprocessor mode) can be selected with the fol-
lowing:
Processor mode bits of the processor mode register 0 (bits 1 and 0
at address 5E16; Figure 11)
Table 9 lists the selection method of a processor mode.
The memory map which the CPU can access depends on the se-
lected processor mode. Figure 13 shows the memory maps in three
processor modes.
Also, the functions of ports P0 to P4, P10, P11, and part of port P9
depend on the selected processor mode. For details, see Table 10.
In the single-chip mode, ports P0 to P4, P10, P11, and P9 function
as I/O ports. In this mode, only the internal area (SFRs, internal
RAM, internal ROM) is accessible.
In the memory expansion and microprocessor modes, external de-
vices assigned in the external memory area can be connected via
buses. Therefore, ports P0 to P4, P10, P11, and part of port P9 func-
tion as I/O pins for the address bus, data bus, bus control signals.
(Some of port functions are selectable.)
In the memory expansion mode, all of the internal area (SFRs, inter-
nal RAM, internal ROM) and external area are accessible. In the mi-
croprocessor mode, the internal area except for the internal ROM (in
other words, SFRs and internal RAM) and the external area are ac-
cessible.
Note that, when the external devices are located to an area where
the internal area and external area overlap, only the internal area
can be read/written; the external area cannot be read/written.
Table 11 lists each bus control signal’s function.
Fig. 11 Bit configuration of processor mode register 0
7
6
543
2
1
0
Processor mode register 0
Processor mode bits
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Do not select.
Interrupt priority detection time select bits
0 0 : 7 cycles of
φ
0 1 : 4 cycles of
φ
1 0 : 2 cycles of
φ
1 1 : Do not select.
Software reset bit
By a write of “1” to this bit, the microcomputer will be reset, and then, restarted.
External bus wait number select bits
0 0 : 0 wait
0 1 : 1 wait
1 0 : 2 wait
1 1 : ALE expansion wait
Clock
φ1 output select bit
0 :
φ1 output is disabled. (P41 functions as an programmable I/O port pin.)
1 :
φ1 output is enabled. (P41 functions as the clock φ1 output pin.)
Address
5E16