參數(shù)資料
型號: M37920FCCHP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 84/158頁
文件大小: 1261K
代理商: M37920FCCHP
31
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
Chip select wait controller
By the control of the chip select wait controller (CSWC), the chip se-
lect function for the maximum of 4 blocks can be set at the bus ac-
cess to the external area.
Also, by the setting of the CSWC, port pins P90 to P93 can operate
as chip select output pins (CS0 to CS3).
Figure 14 shows a chip select output waveform example.
This chip select function determines the following items of the chip
select area: start address, address’s block size, wait number, exter-
nal data bus width, RDY control validity, DRAM specification, burst
ROM specification, and recovery cycle insertion validity.
For the external area except for areas CS0 to CS3, the processor
mode registers 0, 1 determine the above items. After reset is re-
moved, when the microcomputer starts it’s operation in the micropro-
cessor mode, area CS0 is automatically selected.
Table 12 lists the function of areas CS0 to CS3.
Figure 15 shows the bit configuration of the CS0/CS1/CS2/CS3 con-
trol register Ls. These registers determine the following items of a
device to be connected: wait number, external data bus width (Note
1: The external data bus width of area CS0 is determined by pin
BYTE’s level.), RDY control validity, DRAM space specification
(Note 2: For area CS0, this function is invalid.), burst ROM access
specification, recovery cycle insertion validity. For DRAM access,
refer to the section on the DRAM controller.
Figure 16 shows the bit configuration of the CS0/CS1/CS2/CS3 con-
trol register Hs. These registers determine block size of an external
area to be connected. For areas CS1 and CS2, by selecting mode 1
with the area CSk setting mode select bit, an chip select area can be
set to the external area in bank 0.
Figure 17 shows the bit configuration of the area CS0/CS1/CS2/CS3
start address registers. For details of these addresses’ setting, see
Figures 18 to 20.
When area CSi is accessed
φ1
A23 to A0
ALE
RD,
When the same area CSi is accessed sequentially
φ1
A23 to A0
ALE
RD,
Address + 2
One access
cycle
Address
One access
cycle
Address
CSi
BLW, BHW
One access
cycle
CSi
Fig. 14 Chip select output waveform example
q Burst ROM access
For ROM supporting the burst ROM access, the burst ROM access
can be specified. The burst ROM access is valid only when the ex-
ternal data bus width = 16 bits with an instruction prefetched. In the
other cases, the normal access is performed regardless of the con-
tents of the burst ROM access select bit.
Figure 21 shows a waveform example at burst ROM access.
When an instruction is prefetched from the burst ROM, 8 bytes are
fetched starting from an 8-byte boundary (the low-order 3 bits of ad-
dress, A2, A1, A0 = “000”) in waveform (a). When branched, regard-
less of the 8-byte boundary of the branch destination address,
access starting from the 4-byte boundary (the low-order 2 bits of ad-
dress, A1, A0 = “00”) is performed in waveform (b). Once the 8-byte
boundary has been selected, instructions will be prefetched in wave-
form (a) until a branch.
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