參數(shù)資料
型號: M37920FCCHP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 138/158頁
文件大小: 1261K
代理商: M37920FCCHP
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
80
Priority
Priorities are assigned to all DMA channels. Either the fixed or rota-
tive priority can be selected. When bit 0 (priority select bit) of the
DMAC control register is cleared to “0”, the fixed priority is selected.
Note that the fixed priority is automatically selected after the reset
removal. In the fixed priority, the channels are given fixed priorities
and DMA transfer is executed in the order of priority. From high to
low, the priorities are assigned to channels 0, 1, 2, and 3. As indi-
cated in Figure 76, the priorities are detected at each cycle in the
cycle steal transfer mode or when the first DMA request is accepted
in the burst transfer mode.
When bit 0 of the DMAC control register is set to “1”, the rotative pri-
Fig. 75 Rotative priority
Channel 0
Channel 1
Channel 3
Channel 1
Channel 2
Channel 0
Channel 2
Channel 3
Channel 1
Channel 3
Channel 0
Channel 2
(1) Before start of transfer (after reset removal)
(2) After completion of channel 0’s transfer
(3) After completion of channel 2’s transfer
ority is selected. From high to low, the initial priorities are assigned
to channels 0, 1, 2, and 3 as is the case with the fixed priority. When
a DMA transfer for one channel is normally terminated with the rota-
tive priority employed, the priorities are rotated in such a manner that
the channel, for which transfer has just been completed, has the low-
est priority. For example, when channel 0’s transfer is normally ter-
minated as shown in Figure 75, the priorities are rotated upon
completion of transfer so that the new priorities are, in decreasing
order, channel 1, channel 2, channel 3, and channel 0. The priorities
remain unchanged when DMA transfer is forcibly terminated by pin
TC’s input or the DMA enable bit clearance, etc.
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