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參數(shù)資料
| 型號(hào)： | MB86965A |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 16/76頁 |
| 文件大小： | 394K |
| 代理商： | MB86965A |
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MB86965
23
DATA LINK CONTROL REGISTERS
Status and control bits for the EtherCoupler’s Transmitter
and Receiver sections are located in Data Link Control
registers DLCR0 through DLCR7.
Transmit Status Register
As shown in Table 12, this register provides transmit
status for the host processor. The system can enable
interrupts based on setting (active high) of bits 7, 3, 2, or 1
of this register by setting the corresponding interrupt
enable bits in the Transmit Interrupt Enable register,
DLCR4.
Writing 1 to bits 7, 3, 2, and 1 clears this register, which
can generate interrupts. Writing 0 to these bits has no
effect; only EtherCoupler’s control logic can set these
bits. Clearing the bit that causes an interrupt clears the bit
and the interrupt. Because two or more status conditions
may occur simultaneously, the interrupt routine must read
and act on all status conditions that are set.
One method to clear interrupts is to read the contents of
the status register, then write the same value back to the
register, thus clearing all bits that were set. Another
technique is to clear each status bit separately, by writing
its mask (interrupt enable) to the register. This might be
done as the corresponding interrupt service is performed.
Note that wholesale clearing of all status bits by writing
FFH to the register is not recommended, because this
action may clear a just set status that has not yet been read
by the system. Note also that the Transmitter must be idle
and TX DONE, DLCR0<7>, must be cleared by writing
1 to it, before starting the Transmitter by writing 1 to TX
START bit, BMPR10<7>.
Table 12. DLCR0 — Transmit Status Register
BIT
SYMBOL
TYPE
DESCRIPTION
7
TX DONE
RC0
TRANSMIT DONE: This bit is set high when all packets in the active
TRANSMIT BUFFER have been successfully transmitted to the LAN media,
or skipped due to excessive collisions. Can generate interrupts if enabled by
DLCR 2<7>.
6
NET BSY
R
NET BUSY: This is a real-time image of the Carrier Sense signal of the
Receiver.
5
TX PKT
RCD
RC0
TRANSMIT PACKET RECEIVED: Indicates that good packet was received
by EtherCoupler shortly after transmission was completed. This is used to
indicate self-reception of the packet. This bit is cleared as each transmission
begins, or by writing 1 to it.
4
CR LOST
R0
CARRIER LOST: This bit is set if the receive Carrier Sense input is negated
during a packet transmission. This can be caused by collision or a shorted
LAN medium. It is automatically cleared as each transmission begins.
3
JABBER
RC0
JABBER: When active high, indicates excessive transmit length is detected
by Jabber timer. Can generate interrupts if enabled by INT
EN bit,
DCLR2<3>.
2
COL
RC0
COLLISIONS: This bit will assert during transmission of a data packet if a
collision occurs on the network. The Buffer Controller will automatically
re–transmit the current packet after collisions up to 16 times. The user may
read the number of consecutive collisions in collision counter, DCLR4<7:4>.
Can generate interrupts if enabled by INT EN bit, DCLR2<2>.
1
16 COL
RC0
16 COLLISIONS: This bit is set after the sixteenth unsuccessful transmission
of the same packet. Can generate interrupts if enabled by INT EN bit,
DLCR2<1>.
0
R0
RESERVED: Write 0.
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