參數(shù)資料
型號： MB86965A
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝： PLASTIC, QFP-160
文件頁數(shù)： 75/76頁
文件大?。?/td> 394K
代理商： MB86965A
MB86965
8
PIN NO.
SYMBOL
MODE
TYPE
DESCRIPTION
10
X13SEL
0, 1, 2
O
SELECT CONFIGURATION REGISTER 2: Active low signal pulse to
read the jumper configuration register 2, located at address 0X13.
10
SB/SW
3
O
SYSTEM BYTE / WORD BUS WIDTH: When high, System Bus operates
in 8-bit mode; when low,16-bit mode is selected. Same as DLCR6<5>.
12
SK
0, 1
O
EEPROM SHIFT CLOCK: With EEPROM option, this signal is generated
from software, which shifts data in and out of the EEPROM.
12
LSA0
2
O
LATCHED ADDRESS 0: With ID PROM option, the pin provides one of
three latched address lines to the ID PROM.
13
DI
0, 1
O
EEPROM DATA IN: With EEPROM option, this is serial data going to the
EEPROM.
13
LSA1
2
O
LATCHED ADDRESS 1: With ID PROM option, the pin provides one of
three latched address lines to the ID PROM.
14
DO
0, 1
I
EEPROM DATA OUT: With EEPROM option, this is serial data coming
from the EEPROM.
14
LSA2
2
O
LATCHED ADDRESS 2: With ID PROM option, the pin provides one of
three latched address lines to the ID PROM.
11
EPCS
0, 1
O
PROM CHIP SELECT: High signal selects EEPROM.
11
EPCS
2
O
PROM CHIP SELECT: Low signal selects ID PROM.
108
RDYPOL
0, 1, 2,3
I
READY LINE POLARITY SELECT: Controls polarity of IOCHRDY signal
at pin 151, where 0 is active low ready and 1 is active high ready.
108
SMEMWR /
RDYPOL
0, 1, 2
I
MB86965B ONLY: Dual–function pin in ISA–BUS compatible operating
modes 0, 1 and 2 (when one or both of mode pins 91 and 92 are tied low),
pin 108 serves as the ’system memory write’ input (SMEMWR) to support
writing to a Flash Boot ROM (For this purpose, it should be connected to
the system memory write pin of the PC/XT/AT/ISA bus connector.) In
these three modes, the MB86965B will provide chip select pulses to the
boot ROM for both read and write operations. In mode 3, pin 108 reverts
toits original role in the MB86965A as RDYPOL, an input to select the
polarity of the ready pin.
63
RMTCNTRL
0, 1, 2, 3
O
REMOTE CONTROL: When RMT RST bit DLCR5<2> is set high, this pin
follows RMT 0900H bit DLCR1<4>, which indicates that a complete
special packet with type field = 0900H has been received. This is intended
for use as a remotely controlled hardware function from other nodes in the
network.
64
CNTRL
0, 1, 2, 3
O
CONTROL: This pin is intended as a hardware control pin programmable
by the system software. Complement of CNTRL, DLCR4<2>.
127, 129,
143–150,
152, 153
RESERVED
3
I
NOT USED. These pins should be pulled low to ground.
7–9,
11–15,
123, 128
RESERVED
3
O
NOT USED. These pins should be left floating, internally pulled high.
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相關(guān)代理商/技術(shù)參數(shù)
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