參數(shù)資料
型號(hào)： MB86965A
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝： PLASTIC, QFP-160
文件頁數(shù)： 67/76頁
文件大小： 394K
代理商： MB86965A
MB86965
7
PIN NO.
SYMBOL
MODE
TYPE
DESCRIPTION
133
IRQA
0, 1, 2, 3
O
24-ma
tristate
INTERRUPT REQUEST: One of four interrupt request lines which
indicate that EtherCoupler requires host attention after successful
transmission or reception of a packet, or if any error conditions occur,
including an EOP after the completion of the DMA cycle.
130–132
IRQD, IRQC,
IRQB
0, 3
O
24-ma
tristate
INTERRUPT REQUEST: In jumperless mode: three of four interrupt
request lines which indicate that EtherCoupler requires host attention
after successful transmission or reception of a packet, or if any error
conditions occur, including an EOP after completion of DMA cycle.
130–132
MSEL<2:0>
1, 2
I
MEMORY SELECT: In jumper select mode: sets Boot ROM location base
address.
MSEL2
MSEL1
MSEL0
ROM ADDRESS RANGE
0
C4000 – C7FFF
0
1
C8000 – CBFFF
0
1
0
CC000 – CFFFF
0
1
D0000 – D3FFF
1
0
D4000 – D7FFF
1
0
1
D8000 – DBFFF
1
0
DC000 – DFFFF
1
Decode disabled
126
DREQ
0, 1, 2, 3
O
DMA REQUEST: Issued to the DMA controller to indicate that
EtherCoupler has data available to be read in its receive buffer, or is ready
to accept data into its transmit buffer.
151
RDY(RDY)
3
O
24-ma
tristate
INPUT/OUTPUT CHANNEL READY: This signal indicates to the host
that EtherCoupler is ready to complete the requested read or write
operation. Polarity of this pin is programmed by RDYPOL, pin 108.
High-impedance to READY valid, or READy valid to high impedance
(Tables 41 and 43). N-channel open drain.
151
IOCHRDY
0, 1, 2
O
24-ma
tristate
INPUT/OUTPUT CHANNEL READY: This signal indicates to the host
that EtherCoupler is ready to complete the requested read or write
operation. RDYPOL pin must be tied to ground. N-channel open drain.
128
IOCS16
0, 1, 2
O
24-ma
tristate
INPUT/OUTPUT 16-BIT CHANNEL SIZE: Active low signal which
indicates that present data transfer is 16-bit I/O cycle. N-channel open
drain.
123
ENHB
0, 1, 2
O
ENABLE DATA HIGH BYTE: Active low signal which enables the system
data transceiver high byte.
7
ENLB
0, 1, 2
O
ENABLE DATA LOW BYTE: Active low signal which enables the system
data transceiver low byte.
8
DIR
0, 1, 2
O
TRANSCEIVER DIRECTION: Active low signal sets the external
transceiver direction, from chip to system (read operation). Active high
signal sets the external transceiver direction from system to chip (write
operation).
9
X12SEL
0, 1, 2
O
SELECT CONFIGURATION REGISTER 1: Active low signal pulse to
read the jumper configuration register 1, located at address 0X12.
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