參數(shù)資料
型號(hào): MB86965A
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝: PLASTIC, QFP-160
文件頁數(shù): 70/76頁
文件大?。?/td> 394K
代理商: MB86965A
MB86965
72
Table 54. RCLK/End of Frame Timing (Mode 3) — For Reference Only
SYMBOL
PARAMETER DESCRIPTION
MINIMUM
TYPICAL
MAXIMUM
UNITS
tRCH
RCLK hold after CD low
27
bit time
tRD
RCV data throughput delay
275
ns
tCDOFF
CD turn-off delay, measured from middle of last
bit, so that timing specification is unaffected by
the value of the last bit.
375
ns
tIFG
Receive block out
400
bit time
The CD, RCLK and RXD signals are internal to the EtherCoupler chip, and are provided for reference only. The RXD signal
changes at the rising edge of RCLK. The controller is sampled at the falling edge. Typical figures are at 25
°C and are for design
aid only, not guaranteed and not subject to production testing.
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MB88151APNF-G-500-JNE1 OTHER CLOCK GENERATOR, PDSO8
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