參數(shù)資料
型號: MB86965A
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝: PLASTIC, QFP-160
文件頁數(shù): 25/76頁
文件大?。?/td> 394K
代理商: MB86965A
MB86965
31
Table 22. DLCR7 — Configuration Register 1
BIT
SYMBOL
TYPE
DESCRIPTION
7
6
ECID1
ECID0
R1
ETHERCOUPLER IDENTIFICATION: When both set high, indicates to software that
EtherCoupler rather than another Fujitsu product is being used as controller.
5
PWRDN
RW1
POWERDOWN: When set high, enables power to the chip for all functions; when set
low, places chip in powerdown mode for power conservation.
4
RDYPNSEL
R 0/1
READY PIN SELECT: Reads the state of RDYPOL signal at EtherCoupler pin 108.
3
2
RBS1
RBS0
RW0
REGISTER BANK SELECT: Provides the indirect address for selecting one of
three sets of registers to access when the physical register address is xxx8H-
xxxF. The lower seven registers are not bank-selectable.
RBS1
RBS0
Registers
0
DLCR0 thru DLCR7, DLCR8 thru DLCR15
0
1
word
1
0
Do not use
1
byte
1
EOPPOL
RW0
EOP PIN SIGNAL POLARITY: When high, the EOP pin is active-high; when low, EOP
is active-low.
0
M..L / L.M
RW0
BYTE ORDER CONTROL: Selects byte lane ordering for packet data in the buffer
(applies only in System Word mode). In both Most.Least and Least.Most modes, the
first and second bytes of the packet, as well as its non-transmitted buffer header, will
appear in the same word on the system bus. When this bit is high (M..L mode), the first
and all odd-numbered bytes of a packet and its header appear on the high byte of the
system bus. When low, the first and all odd-numbered bytes of a packet appear on the
low byte. Note that header bytes are also swapped.
As shown in Tables 21 and 22, system configuration bits
are found in these two registers. Among the configuration
controls found here are physical memory size, partition-
ing between transmit and receive buffers, widths of
memory and system busses, byte lane control, and
powerdown control. Most configuration parameters are
programmed only during initialization, after power start
and hardware reset.
Software engineers, who want to use the same node driver
for EtherCoupler and NICE controllers from Fujitsu,
should note that the driver can determine which chip is
being used, by reading DLCR7 or DLCR6 after hardware
reset. EtherCoupler reads E0B6H (E0H or F0H for
DLCR7 and B6H for DLCR6, when in byte mode);
NICE reads 30B6H or 20B6H.
Powerdown mode saves power when EtherCoupler is not
in use. When ready to place the EtherCoupler chip in
Powerdown mode, first write 1 to DLC EN, DLCR6<7>,
to turn off the Receiver and Transmitter, then write 0 to
PWRDN, DLCR7<5>. To exit the Powerdown mode,
write 1 to PWRDN. Register contents are preserved,
unless hardware is reset. Hardware reset also terminates
the Powerdown mode.
Byte-order control provided by Most..Least/Least..Most
bit, DLCR7<0>, provides compatibility with various
higher-level protocols, such as TCP/IP and XNS. These
protocols may have a different order for transmission of
the bytes within a word. When M..L/L..M is low, the
least-significant byte of the word transmits first, followed
by the most-significant. When M..L/L..M is set high, the
byte order reverses. This feature applies only when the
system bus operates in 16-bit (word) mode.
The byte-order control works by reversing, or not
reversing, the bytes of all words as they pass between the
buffer memory and the system bus. Thus all data stored in
the Transmit Buffer or retrieved from the Receive Buffer
is affected, including nontransmitted headers. This
control bit does not affect the EtherCoupler’s registers
other than Buffer Memory Port registers, BMPR8 and
BMPR9. When using this feature, ensure the reversal of
header information as well as packet data in the software
driver code. See Table 23 for examples of using
least..most and most..least byte ordering.
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