參數(shù)資料
型號(hào)： MB86965A
元件分類(lèi)： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝： PLASTIC, QFP-160
文件頁(yè)數(shù)： 32/76頁(yè)
文件大?。?/td> 394K
代理商： MB86965A
MB86965
38
Table 27. Collision Action Codes Written to BMPR11
ACTION CODE
ACTIONS
02H or 03H
MODE SETUP: Halt after 16 collisions.
02H
COMMAND: Resume transmitting, repeat failed packet. For use following a halt. Terminates the halt.
Instructs Transmitter to resume transmitting by repeating the failed packet. The collision counter is
reset, allowing up to 16 additional attempts to be made. Transmitter will again halt after 16 collisions.
03H
COMMAND:
Resume transmitting, skip failed packet. For use following a halt. Terminates the halt.
Instructs Transmitter to skip the failed packet and resume transmitting with the next packet in the buffer.
The collision counter is reset, allowing up to 16 additional attempts to be made. If there is no next packet,
the Transmitter deactivates, setting TX DONE bit, DLCR0<7>, as it does so. Transmitter halts after 16
collisions.
06H
MODE SETUP: Continue automatically after 16 collisions, repeat failed packet. Note that if the network
medium disconnects, transmission attempts usually result in false collision detection. Under this
condition, this mode causes Transmitter to continue attempting transmission of the same packet
indefinitely. Interrupt or periodic polling of the status bits could detect this condition.
07H
MODE SETUP: Continue automatically after 16 collisions, skip failed packet. Note that this mode
results in failure to transmit some packets, because it skips a packet that has had 16 consecutive
collisions. While this condition is rare on a healthy network, it does occur occasionally.
DMA Enable Register
Table 28. BMPR12 — DMA Enable Register
BIT
SYMBOL
TYPE
DESCRIPTION
7 – 2
0
RESERVED: Write 0.
1
RX DMA EN
WR0
DMA RECEIVE ENABLE: When set to 0, disables DMA read. When set to 1, enables
DMA read.
0
TX DMA EN
WR0
DMA TRANSMIT ENABLE: When set to 0, disables DMA write. When set to 1, enables
DMA write.
RX DMA EN TX DMA EN
ACTIONS
0
Clear or terminate DMA activity, DMA EOP status bit and
associated interrupt, if any. Normally used as response to
End of Process (DMA EOP) interrupt.
0
1
Enable Transmit Write DMA.
1
0
Enable Receive Read DMA.
Table 28 describes DMA Enable register, BMPR12, a
write-only register that enables or clears Receive Read
DMA or Transmit Write DMA.
Table 29 describes DMA Burst and XVR Mode register,
BMPR13, which selects the burst length for DMA
operation, and programs the 10BASE-T Transceiver
modes. Each burst is one word or one byte, depending on
System Byte/System Word mode selected, DLCR6<5>.
Writing code 00H, 01H, 02H or 03H to the register selects
burst length as 1, 2, 4, or 12 transfers.
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