參數(shù)資料
型號(hào)： MB86965A
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝： PLASTIC, QFP-160
文件頁數(shù)： 56/76頁
文件大?。?/td> 394K
代理商： MB86965A
MB86965
6
SYSTEM BUS TO INTERFACE PINS
PIN NO.
SYMBOL
MODE
TYPE
DESCRIPTION
112–115
117–119
122
157–159
2–6
SD<15:12>
SD<11:9>
SD<8>
SD<7:5>
SD<4:0>
0, 1, 2, 3
I/O
SYSTEM DATA: All data, command, and status transfers take place over
this bus.
150–145
144–141
139–134
SA<19:14>
SA<9:6>
SA<5:0>
0, 1, 2
I
SYSTEM ADDRESS: Selects EtherCoupler internal register or port for
read/write operations.
137–134
SA<3:0>
3
I
SYSTEM ADDRESS: Selects EtherCoupler internal register or port for
read/write operations.
142
141
INTSEL0
INTSEL1
3
I
INTERRUPT SELECT: Selects the interrupt signal. Read only. Same as
BMPR19<6:7>.
139
127
SBHE
3
0, 1, 2
I
SYSTEM BUS HIGH ENABLE: Active low. This pin is the byte/word
control line. It is used only when EtherCoupler is configured for a 16-bit
data bus by the SB/SW bit, DLCR6<5>. It allows word, upper byte only or
lower byte only transfers. The address select pin SA0 is used with SBHE
for byte or word transfers as follows:
SB/SW
SBHE
SA0
FUNCTION
0
Word transfer
0
1
Byte transfer on upper half of
data bus (SD15-8)
0
1
0
Byte transfer on lower half of
data bus (SD7-0)
0
1
Reserved
1
X
Byte transfer (SD7-0)
138
CS
3
I
CHIP SELECT: Active low signal which, when set to 0, selects the
EtherCoupler chip.
156
RESET
0, 1, 2, 3
I
CHIP RESET: Resets the chip internal pointers and initializes internal
registers and logic.
154
IOR
0, 1, 2, 3
I
INPUT/OUTPUT READ: Active low signal from the system bus which
indicates that the current bus cycle is a read operation.
155
IOW
0, 1, 2, 3
I
INPUT/OUTPUT WRITE: Active low signal from the system bus which
indicates that the current bus cycle is a write operation.
153
SMEMRD
0, 1, 2
I
SYSTEM MEMORY READ: Active low signal from the system bus that
indicates the current bus cycle is in a memory-read operation. Used for
Boot ROM Chip Select (BRCS).
152
AEN
0, 1, 2
I
ADDRESS ENABLE: When asserted indicates that a DMA transfer is
taking place.
124
EOP(EOP)
0, 1, 2, 3
I
END OF PROCESS: When asserted by the DMA controller, indicates that
an entire packet has been transferred between buffer memory and the
host system.
129
ALE
0, 1, 2
I
ADDRESS LATCH ENABLE: Provided by the system to latch valid
addresses.
125
DMACK
0, 1, 2, 3
I
DMA ACKNOWLEDGE: Active low signal which indicates that the DMA
controller is ready to transfer data between the host system and the
EtherCoupler buffer memory.
15
BRCS
0, 1, 2
O
BOOT ROM CHIP SELECT: Active low signal which indicates that the
current memory access is to Boot ROM.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MB86965B 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER
MB86965BPF-G-BND 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER
MB86967 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces
MB86967PFV 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces
MB86977 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IP PACKET FORWARDING ENGINE
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