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| 型號： | MB86965A |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 35/76頁 |
| 文件大?。?/td> | 394K |
| 代理商： | MB86965A |
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MB86965
40
Filter Self Receive Register (BMPR14)
Table 30. BMPR14 — Filter Self Receive Register
BIT
SYMBOL
TYPE
DESCRIPTION
7
INT EN
RC0
INTERRUPT ENABLE: When high, enables RLD, BMPR15<7>, to generate an
interrupt.
6
INT EN
RC0
INTERRUPT ENABLE: When high, enables LLD, BMPR15<6>, to generate an
interrupt.
5
INT EN
RC0
INTERRUPT ENABLE: When high, enables RJAB, BMPR15<5>, to generate an
interrupt.
4
0
RESERVED: Write 0
3
0
RESERVED: Write 0
2
SKIP PKT
WR0
SKIP RECEIVE PACKET: Flushes one receive packet. EtherCoupler adjusts the
system read pointer to the beginning of the next received packer. The new pointer
points to an empty buffer if there are no incoming packets, and remains uncharged if it
points to an empty packet.
1
INT EN
RC0
INTERRUPT ENABLE: When high, enables SQE, DLCR15<1>, to generate an
interrupt.
0
FILTER
SELF RX
WR1
FILTER SELF RECEIVE: When set to 1, disables the Accept All Packets mode Self
Receive function. When set to 0, enable the self receive function in Accept All Packets
mode.
Table 30 describes Filter Self Receive register, BMPR14.
[Also refer to Table 20 and the detailed description of
Receive Mode register, DLCR5, for more information
about the Filter Self Receive function.]
Writing 04H to this register commands the Buffer
Controller to skip the balance of the current receive
packet in memory. The bit can then be read to determine
completion of the skip process is complete (within 300
ns). If there is another packet, the bit returns to 0 when the
chip is ready to read the next packet or, if there is not
another packet, to stop reading. Do not use this feature
before reading at least four times from the beginning of
the packet, nor if there are eight or fewer bytes left of the
packet in the buffer; doing so may corrupt the receive
buffer pointers.
Regardless of whether EtherCoupler is in byte or word
mode, the system has to read four times from the receive
buffer so that the SKIP PKT function can operate
properly. The SKIP PKT function cannot be used when
the receive packet contains only two bytes when the
system in byte mode, or two words when the system in
word mode. Those bytes or words move into system
FIFO, and the System Read Pointer points at the next
packet location.
As shown in Table 30, this register provides control for
enabling interrupts based on the setting of status bits in
BMPR15, the Transceiver Status Register.
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