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| 型號： | MB86965A |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 4/76頁 |
| 文件大?。?/td> | 394K |
| 代理商： | MB86965A |
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MB86965
12
SYSTEM INTERFACE
GENERAL
The System Interface provides the interface logic
necessary to connect to a PC/XT/AT/ISA bus and, via an
alternate bus mode, to an x86, RISC or 680 x 0-type
microprocessor bus. The interface supports 8- and 16-bit
bus widths and byte or word transfers, as determined by
the SB/SW bit, DLCR6<5>. Depending on the type of
host CPU, EtherCoupler supplies the data order, MSB or
LSB first (big or little endian), according to the setting of
the M..L/L..M bit, DLCR7<0>.
EtherCoupler supports I/O-mapping, and burst or
single-transfer DMA modes. The user can select the
active interrupt pin to inform the CPU of transmit and
receive status conditions requiring host processing.
EtherCoupler includes three sets of user-accessible
registers, all of which are accessible as bytes or words.
Pins 90 to 92 allow selection and configuration of the
mode in which the MB86965 operates. Specifically,
when MODE<2:0> bits are set to 00H, the bus is in ISA
mode with an EEPROM that stores initial parameters and
jumperless operation. When MODE<2:0> bits are set to
01H the bus is set for operation with jumpers and
EEPROM. When MODE<2:0> bits are set to 02H the bus
is set for operation with jumpers and ID PROM. When
MODE<2:0> bits are set to 03H the bus is set for generic
bus operation.
REGISTER ACCESS
Direct access is available to eight registers in the device’s
register set, addresses xxx0H through xxx7H. Access to
remaining physical addresses is through indirect
addressing or bank-switching of three different register
banks, for the address set xxx8H through xxxFH.
Bank-switching bits reside in register 07H. The
bank-switched register group comprises three sets of
banks of registers: Node ID (Ethernet Address) and TDR
Diagnostics; Hash Table for multicast address filtering;
and Buffer Memory Access. During normal operation
(excluding initialization or diagnostics), the Buffer
Memory Access bank is selected, and access to other
registers is not required.
BUFFER ACCESS
The Buffer Memory Port register pair BMPR8 and
BMPR9 provide 8 or 16-bit data width access to the
receive and transmit buffers through on-chip FIFOs. To
eliminate the need for complicated directional control,
FIFOs are dedicated to each direction of data transfer.
Writing to the transmit buffer interleaves with reading
from the receive buffer, with EtherCoupler automatical-
ly maintaining buffer memory pointers. The Buffer
Memory port register pair is accessible via register
address xxx8H, when bank I is selected. When using
DMA, the buffer memory port is automatically selected
when the DMA Acknowledge input, DMACK is
asserted.
Data can transfer from the host memory to the transmit
buffer, or from the receive buffer to host memory by
using string moves, single-transfer programmed I/O
moves, or DMA. Select the method that yields the highest
system-level efficiency. A rapid transfer process results in
best performance. Slow transfer could result in poor
throughput and performance, and cause the receive
buffer to overflow and lose packets.
I/O OPERATION
Write transmits data to BMPR10, and I/O Write will
address the data to the Transmit Buffer. Read receives
data on BMPR10 through I/O Read, which will load the
data from the Receive Buffer.
DMA OPERATION
EtherCoupler supports single-cycle and burst DMA
operation for data transfer between the host system and
the dedicated buffer memory. Handshaking between
EtherCoupler and external DMA is accomplished by the
DREQ and DMACK signals. The end of process input,
pin 124, when asserted by the system DMA controller
during a transfer cycle, terminates DMA activity after
completion of the current cycle. If a DMA interrupt
(DLCR3<5>) is enabled, EtherCoupler generates an
interrupt after completion of DMA activity.
DMA Write (Transmit)
Setting the TX DMA Enable bit, BMPR12<0>, enables
DMA transfer of data packets from the host memory to
the EtherCoupler transmit buffer. When invoked, DMA
burst control bits BMPR13<1:0> enable burst transfers.
EtherCoupler, when ready to accept data from the host,
sets the DMA request output, DREQ, and the host
responds by setting DMA acknowledge, DMACK, and
write enable, WE, and placing data on the data bus.
EtherCoupler sets the IOCHRDY output when ready to
complete the current data-transfer cycle. (Polarity of the
IOCHRDY signal and the EOP input are independently
programmable.) EtherCoupler accepts the data byte/
word into its Bus Write FIFO and later moves it into
buffer memory. At the close of a transfer cycle, the host
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MB86965B | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER |
| MB86965BPF-G-BND | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:EtherCoupler ETHERNET CONTROLLER WITH 10BASE?T TRANSCEIVER |
| MB86967 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces |
| MB86967PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:LAN Controller with PC Card, ISA Bus, and General-purpose Bus Interfaces |
| MB86977 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IP PACKET FORWARDING ENGINE |
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