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參數(shù)資料
| 型號： | MB86967PFV |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 45/129頁 |
| 文件大小： | 1519K |
| 代理商： | MB86967PFV |
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22
MB86967
7. Buffer Controller
7.1 General
The MB86967 uses a dedicated buffer memory, organized as shown in Figure 2, for intermediate storage of
packets to be transmitted, and of packets received from the network. The MB86967 can operate with 8 or 32
kilobytes of total buffer memory, including both transmit and receive spaces. Memory partitioning into transmit
and receive sections is controlled by the system software. The total size of the transmit buffer space can be up
to 16 kilobytes. The buffer memory not used for the transmitter is used for the receiver, and is automatically
configured as a ring buffer. Packets are stored head-to-toe in the receive buffer, as they are in the transmit buffer.
However, each packet in the receive buffer is aligned on an eight-byte boundary. As packets are being stored
in the receive buffer, as the end of the linear addressing space is reached, the chip’s receive write pointer
automatically wraps around to the top of the receive addressing range to make a seamless ring. The receive
read pointer does the same as the packets are read out to the system. By programming the sizes allocated to
transmit and receive buffers, an optimum usage of the memory can be selected according to the demands of a
particular application.
The buffer controller keeps track of buffer memory partitioning and allocation and updates internal address
pointers automatically for the tasks of transmit, retransmit, receive, rejection of packets with errors and data
transfers to and from the host. The host and its drivers are thus relieved of buffer management functions, making
the MB86967 easy to operate and substantially reducing software requirements. Packets with errors are normally
automatically rejected by the MB86967 as are packets shorter than the IEEE minimum length packet of 60 bytes,
excluding Preamble and CRC. Since these tasks can be done faster in hardware than in software, this not only
TRANSMIT BUFFERS
RECEIVED PACKET n+3
(LAST PART)
CURRENTLY AVAILABLE
FREE BUFFER AREA
RECEIVED PACKET n
RECEIVED PACKET n+1
RECEIVED PACKET n+2
RECEIVED PACKET n+3
(FIRST PART)
ONE OR TWO
TRANSMIT BUFFER
RECEIVE BUFFER RING
(30 KILOBYTES MAX)
Figure 2 Buffer Memory Organization
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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