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參數(shù)資料
| 型號(hào)： | MB86967PFV |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, LQFP-100 |
| 文件頁(yè)數(shù)： | 46/129頁(yè) |
| 文件大?。?/td> | 1519K |
| 代理商： | MB86967PFV |
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MB86967
off-loads the host system, but it also speeds up the communication processes, yielding higher throughput. As
a result, the MB86967 can typically win benchmark performance tests over competing controllers.
7.2 Arbitration of Buffer Access
The buffer controller automatically prioritizes and services requests for access to memory from the transmitter,
receiver and host system. The MB86967’s arbitration mechanism, illustrated in Figure 3, interleaves accesses
to the buffer memory so that the operation appears to be simultaneous: data can be written to or read from the
buffer memory by the host via Buffer Memory Port Register 8 (BMPR8), while data is being read from the buffer
by the transmitter and/or written in for storage by the receiver. Each interface, whether host system or network
access, appears to be served independently by the controller. Each interface has an associated FIFO to provide
time for the buffer interleaving. Thus, packet data is pipelined through the system for highest performance and
throughput, and the buffer controller supports all the cases of simultaneous access to the buffer memory as
follows:
1. Data from the network is stored in the receive buffer.
2. The host retreives packets from the receive buffer.
3. The host loads packet data into the transmit buffer.
4. The transmitter obtains data for transmission from the transmit buffer.
5. Any combination of the above can occur concurrently.
7.3 Transmit Buffer
The section of the memory used by the transmitter can be configured by programming the Transmitter Buffer
Size control bits, DLCR6<3:2>. Configurations include a single buffer 2 kilobytes long, or a pair of banks, each
either 2, 4 or 8 kilobytes long, as illustrated in Figure 4. Within each buffer or bank, one or more packets can be
written by the system until the available space is too small for another packet. When a single transmit buffer is
used, the system and the transmitter time-share the use of the buffer. When two buffers are used, the system
can load packets into one of the buffers while the contents of the other are being transmitted. Using dual buffers
and loading multiple packets for ’packet chaining’ gives the highest rate of transmission.
HOST CPU
READ
OR
WRITE
MB86967
BUFFER
CONTROLLER
TRANSMIT
RECEIVE
INTERLEAVED
DATA
DEDICATED
BUFFER MEMORY
Figure 3 Simultaneous Access to Buffer Memory
NETWORK
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB86977 | 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:IP PACKET FORWARDING ENGINE |
| MB86977PFV-G-BND | 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:IP PACKET FORWARDING ENGINE |
| MB86A21PMC-G-BNDE1 | 制造商:FUJITSU 功能描述: |
| MB86A21PMC-G-JNE1 | 制造商:FUJITSU 功能描述: |
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