參數(shù)資料
型號: MB86967PFV
元件分類: 微控制器/微處理器
英文描述: 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝: PLASTIC, LQFP-100
文件頁數(shù): 77/129頁
文件大?。?/td> 1519K
代理商: MB86967PFV
51
MB86967
(4) BMPR12: DMA Enable Register
The BMPR12 controls DMA transfer between the host system and the MB86967.
*1: The DLCR1 DMAEOP bit is cleared if the DMA RENA bit and DMA TENA bit are set to “00”.
*2: Writing “11” to both DMA RENA bit and DMA TENA bit is prohibited.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read
××××
LONGPKT
RCV DIS
0
DMA
RENA
DMA
TENA
Write
0000
Initial
Value
××××
0000
Bit no.
Bit name
Operation
Value
Function
7 to 4
Not used
Read
The read values of these bits are always undefined.
Write
0
Writing 1 is prohibited. Always write 0 at writing.
3
LONGPKT RCV
DIS
Read/Write
0
The receive long packet removal function is enabled.
Packets with a length of 1792 bytes or more are not received.
1
The receive long packet removal function is disabled.
Packets with a length of up to 2047 bytes cannot be received
normally.
2
Not used
Read/Write
The read value of this bit is always 0.
Writing 1 is prohibited. Always write 0 at writing.
1
DMA RENA
Read/Write
0 (*1)
DMA read operation is disabled.
* : Writing 1 to this bit is
prohibited in the PC
card mode. Always
write 0 to this bit.
1 (*2)
DMA read operation (reading from
receiver buffer) is enabled.
0
DMA TENA
Read/Write
0 (*1)
The DMA write operation is
disabled.
1 (*2)
The DMA write operation (writing to
receiver buffer) is enabled.
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