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參數(shù)資料
| 型號： | MB86967PFV |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 62/129頁 |
| 文件大小： | 1519K |
| 代理商： | MB86967PFV |
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38
MB86967
(2) DLCR1: Receive Status Register
DLCR1 indicates the receive status of the data link controller. The external interrupt INT is asserted by setting
the bits of DLCR3 corresponding to the status bits, bit 7 to 0.
(Continued)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read
PKT RDY
BUS RD
ERR
DMA
EOP
RMT RST
RX SRT
PKT
ALG ERR CRC ERR OVRFLO
Write
BIT CLR
Initial Value
00000000
Bit no.
Bit name
Operation
Value
Function
7PKT RDY
(Packet Ready)
Read
0
No received packet is in the receiver buffer.
1
Indicates packets from self office received normally and
transferred completely to receiver buffer.
In other words, at least one packet of receive data is in the
receiver buffer.
Write
0
Not affected
1
This bit is cleared. If there are still received packets in the
receiver buffer even after the host system has read one
packet of receive data from the receiver buffer, this bit is
automatically reset.
6BUS RD ERR
(Bus Read
Error)
Read
0
No bus read error
1
Indicates LSI failed to assert RDY signal within 2.15
s at
reading data in receiver buffer from host system.
In other words, the host system attempted to read data from
the receiver buffer, although the buffer has no data to read.
Write
0
Not affected
1
This bit is cleared.
5
DMA EOP
Read
0
Indicates DMA transfer not yet
completed during DMA transfer.
This bit is cleared when both the
DMA RENA and DMA TENA bits of
the BMPR12 are cleared.
* : This bit is invalid in the
PC card mode.
1
Indicates DMA transfer completed
and EOP signal asserted by
external DMA controller
Write
0
Not affected
1
This bit is cleared. This clearing
should be done by clearing both the
DMA RENA and DMA TENA bits of
the BMPR12.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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| MB86A21PMC-G-JNE1 | 制造商:FUJITSU 功能描述: |
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