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參數(shù)資料
| 型號(hào)： | MB86967PFV |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, LQFP-100 |
| 文件頁(yè)數(shù)： | 48/129頁(yè) |
| 文件大?。?/td> | 1519K |
| 代理商： | MB86967PFV |
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MB86967
7.5 Receive Buffer
Once initialized and enabled, the receiver will automatically load any error-free incoming packets which pass
the address filter into the receive buffer through an on-chip FIFO. An interrupt can be provided to alert the host
processor that a packet is available in the buffer. The host processor can read out received packets as they
become available. Continuous reception can continue as long as the receive buffer does not become full. If the
host processor reads the receive packets from the buffer promptly, the buffer will not fill up. If overflow does
occur, the receiver will stop and an interrupt will be generated to indicate the problem. If this occurs, the buffer
should be emptied so that reception can resume. As soon as space becomes available in the receive buffer, the
receiver will automatically resume reception.
The receive buffer size can vary between a maximum of 30 kilobytes when 2 kilobytes are allocated for the
transmit section and a 32 kilobyte SRAM is used, to a minimum of 4 kilobytes if 4 kilobytes are allocated for the
transmit section and an 8 kilobyte SRAM is used. The receive section dynamically allocates space for each
individual incoming data packet, aligning each at an eight-byte ‘page’ boundary. Each received packet is
preceded by a four byte header which provides packet status and the length of that data packet. The data packets
are linked or chained by internal pointers which use the length value in the packet header to calculate the starting
address of the next packet. This buffer format is shown in Figure 6. Since the MB86967 controls its dedicated
BANK0
BANK1
BANK0
TRANSMIT
SECTION
RECEIVE
SECTION
TRANSMIT
SECTION
RECEIVE
SECTION
2KILOBYTES
6KILOBYTES
2KILOBYTES
4KILOBYTES
BANK0
BANK1
BANK0 2KILOBYTES
30KILOBYTES
2KILOBYTES
28KILOBYTES
TRANSMIT
SECTION
RECEIVE
SECTION
TRANSMIT
SECTION
RECEIVE
SECTION
BANK0
BANK1
BANK0
BANK1
4KILOBYTES
8KILOBYTES
16KILOBYTES
24KILOBYTES
TRANSMIT
SECTION
RECEIVE
SECTION
TRANSMIT
SECTION
RECEIVE
SECTION
Figure 4 Transmit Buffer Configurations
Using 8k
× 8 SRAM
Using 32k
× 8 SRAM
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| MB89123APFM | 8-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PQFP48 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB86977 | 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:IP PACKET FORWARDING ENGINE |
| MB86977PFV-G-BND | 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:IP PACKET FORWARDING ENGINE |
| MB86A21PMC-G-BNDE1 | 制造商:FUJITSU 功能描述: |
| MB86A21PMC-G-JNE1 | 制造商:FUJITSU 功能描述: |
| MB86A22PMC-ES-BNDE1 | 制造商:FUJITSU 功能描述: |
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