- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄69018 > MB86967PFV 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 PDF資料下載
參數(shù)資料
| 型號(hào)： | MB86967PFV |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, LQFP-100 |
| 文件頁(yè)數(shù)： | 57/129頁(yè) |
| 文件大?。?/td> | 1519K |
| 代理商： | MB86967PFV |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)當(dāng)前第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)
33
MB86967
10.2 Transmitter Circuits
The transceiver’s transmitter section receives the encoded data from the Manchester encoder and the twisted-
pair network via the TPO circuit. Advanced integrated pulse-shaping produces an output signal that is
predistorted and prefiltered to meet the 10BASE-T jitter template on the TPON and TPOP pins.
During idle periods, the MB86967 transmits link integrity test pulses on the TPO circuit if LINK TEST EN,
BMPR13<5>, is asserted.
10.3 Jabber Control
An on-chip watchdog timer prevents the chip from locking into a continuous transmit mode. When a transmission
exceeds the maximum time limit (specified for the MB86967 as 20 to 150 msec), the watchdog timer disables
the transmit and loopback functions and asserts the JABBER error status bit, DLCR0<3>, generating an interrupt
if so enabled. Before the MB86967 can exit the jabber state, the transmit data circuit must remain idle for between
0.25 and 0.75 seconds.
10.4 SQE Test
The transceiver supports the signal quality error (SQE) test function specified in the standard. After every
successful transmission on the 10BASE-T network, the MB86967 transceiver section transmits the SQE signal
to the controller for 10
±5 bit times over the internal CI circuit. BMPR15<1> reflects the status of this SQE test.
10.5 Receive Input Circuits
Valid received signals from the twisted-pair network connection (the TPI circuit) pass through on-chip filters to
the data decoder.
An internal intelligent squelch function discriminates noise from link test pulses and valid data streams. The
receiver is activated only by valid data streams above the squelch level and with proper timing. If the differential
signal at the TPI circuit inputs falls below 75% of the threshold level (unsquelched) for eight bit times (typical),
the receiver enters the idle state.
10.6 Data Decoder
The data decoder section performs three functions on the received data: clock recovery, carrier detection, and
Manchester data decoding. Carrier detection is indicated to the receiver section by assertion of the internal
carrier sense signal, which occurs shortly after the received data signals appear. Carrier sense status can be
monitored via DLCR0<6>. Clock recovery and data separation are accomplished by an internal phase-locked
loop. The recovered clock is supplied to the receiver together with the recovered NRZ serial data stream.
10.7 Reverse Polarity
The transceiver polarity reverse circuit uses link pulses and end-of-frame data to determine the polarity of the
received signal. A reversed polarity condition is detected when eight opposite receive link pulses are detected
without receipt of a link pulse of the expected polarity. Reversed polarity is also detected if four frames are
received with a reversed start-of-idle. Whenever polarity is reversed, these two counters are reset to zero. If the
transceiver enters the link fail state and no valid data or link pulses are received within 96 to 128 milliseconds,
polarity resets to the default uninverted condition. If Link Integrity testing is disabled, polarity detection is based
only on received data.
The transceiver automatically corrects reversed polarity. Polarity reversal is reported via BMPR15<3>.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB881631BPN-G-ERE1 | 26 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| MB881631BPN-G-EFE1 | 26 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| MB881631CPN-G-ERE1 | 42 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| MB89123APFM | 8-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PQFP48 |
| MB89202P-SH | 8-BIT, MROM, 12.5 MHz, MICROCONTROLLER, PDIP32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB86977 | 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:IP PACKET FORWARDING ENGINE |
| MB86977PFV-G-BND | 制造商:FUJITSU 制造商全稱(chēng):Fujitsu Component Limited. 功能描述:IP PACKET FORWARDING ENGINE |
| MB86A21PMC-G-BNDE1 | 制造商:FUJITSU 功能描述: |
| MB86A21PMC-G-JNE1 | 制造商:FUJITSU 功能描述: |
| MB86A22PMC-ES-BNDE1 | 制造商:FUJITSU 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。