
43
MB86967
(6) DLCR5: Receive Mode Register
DLCR5 sets the receiver operation mode, and displays the status of the receiver buffer memory.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read
TST2
BUF EMP
ACPT
BAD PKT
ADD
SIZE
ENA SRT
PKT
ENA
RMT RST
AM1
AM0
Write
0—
Initial Value
01000001
Bit no.
Bit name
Operation
Value
Function
7TST2
(Chip Test 2)
Read/Write
—
This is a chip test bit. Always write 0 to this bit at writing to
DLCR5. Writing 1 to this bit is prohibited during normal
operation.
6BUF EMP
(Buffer Empty)
Read
0
Indicates valid data remaining in receiver buffer memory
1
Indicates no valid data in receiver buffer memory
Write
—
Not affected
5
ACPT BAD PKT
(Bad Packet
Receive)
Read/Write
0
If the received packet has short packet, alignment, and CRC
errors, it is discarded and is not transferred to the receiver
buffer.
1
A packet with short packet, alignment, and CRC errors is
transferred to the receiver buffer like a normally-received
packet.
4ADD SIZE
(Address Size)
Read/Write
0
Compares destination addresses of receive packet and ID
addresses of node for match at all 6 bytes (48 bits)
1
Compares destination addresses of received packet and ID
addresses of node for match only at upper byte and 5 bytes
(40 bits)
3
ENA SRT PKT
(Enable Short
Packet Receive)
Read/Write
0
A packet of more than 60 bytes and less than 2 Kbytes can be
received.
1
A packet of more than 6 bytes and less than 2 Kbytes can be
received.
The value of this bit is ignored when bit 5 (ACPT BAD PKT) is
set.
2
ENA RMT RST
(Enable Remote
Reset)
Read/Write
0
The remote reset packet is not detected.
1
Checks whether value of data length field in receive packet is
0900H
1 and 0 AM1, AM0
(Address
Match Mode)
Read/Write
—
Selects node ID address match detect mode at packet
receiving (Tables 3 and 4)