參數資料
型號： MC68HC05C0FN
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 4 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數： 22/96頁
文件大小： 357K
代理商： MC68HC05C0FN
MOTOROLA
Section 4: Interrupts
Page 20
MC68HC05C0 Specification Rev. 1.2
4.1
HARDWARE CONTROLLED INTERRUPT SEQUENCE
The following three functions (RESET, STOP, and WAIT) are not in the strictest sense an
interrupt; however, they are acted upon in a similar manner. Flowcharts for hardware
interrupts are shown in Figure 4-1 : Interrupt Flowchart, and for STOP and WAIT in
Figure 6-2 : STOP/WAIT Flowchart. A discussion is provided below.
1. RESET - Five different reset mechanisms can cause the MCU to vector
to its starting address which is specified by the contents of memory
locations $FFFE and $FFFF. The I bit in the condition code register is also
set. Much of the MCU is configured to a known state during Reset. See
Section 5 RESETS for a description of reset mechanisms.
2. STOP - The STOP instruction causes the oscillator to be turned off and
the processor to “sleep” until an external interrupt (IRQ), a KEY interrupt
or Reset occurs.
3. WAIT - The WAIT instruction causes all processor clocks to stop, but
leaves the timer clock running. This “rest” state of the processor can be
cleared by Reset, an external interrupt (IRQ), a SCI interrupt, a TIM
interrupt, a KEY interrupt, or a MFT interrupt.
4.2
SOFTWARE INTERRUPT (SWI)
The SWI is an executable instruction and a non-maskable interrupt: it is executed
regardless of the state of the I bit in the CCR. If the I bit is zero (interrupts enabled), SWI
executes after interrupts which were pending when the SWI was fetched, but before
interrupts generated after the SWI was fetched. The interrupt service routine address is
specified by the contents of memory locations $FFFC and $FFFD.
4.3
EXTERNAL INTERRUPT
The interrupt request is latched immediately following the falling edge of IRQ. It is then
serviced as specified by the contents of $FFFA and $FFFB.
Either a level and edge-sensitive trigger option, or an edge-sensitive-only trigger option is
one-time writable (at reset) in the External Interrupt Control/Status Register. In addition,
this register also provides enable, request and acknowledge bits for the IRQ. The enable
bit (IRQEN) allows the IRQ interrupt to be masked without having to set the I bit. The
request bit (IRQF) indicates that an IRQ request is pending. The IRQ acknowledge bit
(IRQA) allows a pending IRQ interrupt to be cleared without having to enter the IRQ
more details.
NOTE:
The internal interrupt latch is automatically cleared in the first part of the
interrupt service routine; therefore, one external interrupt pulse could be
latched and serviced as soon as the I bit is cleared.
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