參數(shù)資料
型號(hào)： MC68HC05C0FN
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 4 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 72/96頁
文件大?。?/td> 357K
代理商： MC68HC05C0FN
Section 12: Serial Communications Interface
MOTOROLA
Page 65
MC68HC05C0 Specification Rev. 1.2
NOTE:
The Serial Communications Data Register (SCDAT) is controlled by the
internal R/W signal. It is the transmit data register when written and
receive data register when read.
12.4
RECEIVER
This section describes the receiver wake-up features, the receiver functionality including
the sampling of the bits, and the condition of a start-bit following a framing error.
12.4.1
SCI RECEIVER WAKE-UP FEATURE
In a typical multiprocessor configuration, the software protocol will usually identify the
address(es) at the beginning of the message. In order to permit uninterested MPU’s to
ignore the remainder of the message, a wake-up feature is included whereby all further SCI
receiver flag (and interrupt) processing can be inhibited until certain conditions are detected
on the line. To enable the wake-up feature the RWU bit in SCCR1 must be set. See Section
12.4.1.1
SCI RECEIVER IDLE WAKE-UP
The receiver idle wake-up feature is included whereby all further SCI receiver flag (and
interrupt) processing can be inhibited until its data line returns to the idle state.
An SCI receiver is re-enabled by an idle string of 10 (M=0) or 11 (M=1) consecutive ones.
Software for the transmitter must provide the required idle string between consecutive
messages and prevent it from occurring within messages.
The wake-up method is selected by the WAKE bit. See Section 12.6.2 SERIAL
12.4.1.2
SCI RECEIVER ADDRESS MARK WAKE-UP
A second wake-up method is provided in lieu of the idle string discussed in the previous
section. This method allows the user to insert a logic one in the most significant bit of the
transmit data word (address byte) which will wake up sleeping receivers. In software,
receivers can then compare the received address to determine if they need to listen. If not
they can be put back to sleep and ignore incoming data until the next address mark.
12.4.2
RECEIVE DATA IN
Receive data in (RDI) is the serial data which is transferred from the input pin via the SCI
to the receive data register (RDR). The RDI pin contains an internal Schmitt trigger to
improve noise immunity. While waiting for a start bit, the receiver samples the input at a
rate 16 times higher than the set baud rate. This increased period is referred to as the RT
period. When the input (idle) line is detected low, it is tested for three more sample times
(all data samples are at RT clock edges). If at least two of these three samples detect a
logic low, a valid start bit is assumed to be detected. If in two or more samples, a logic high
is detected, the start bit will be rejected (the line is assumed to be idle), and the next zero
detected will be checked the same way.
相關(guān)PDF資料
PDF描述
MC68HC05C12AFN 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44
MC68HSC05C12AB 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PDIP42
MC68HSC05C12ACP 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PDIP40
MC68HC05C12ACFN 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC44
MC68HSC05C12ACFB 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQFP44
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC68HC05C12 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNITS
MC68HC05C12B 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNITS
MC68HC05C12CP 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNITS
MC68HC05C12P 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNITS
MC68HC05C4 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:8-Bit Microcomputers
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*