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參數(shù)資料
| 型號： | MC68HC05C0FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 4 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 38/96頁 |
| 文件大?。?/td> | 357K |
| 代理商： | MC68HC05C0FN |
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MOTOROLA
Section 8: System Configuration
Page 34
MC68HC05C0 Specification Rev. 1.2
8.2.2
GENERAL - PURPOSE CHIP SELECT TYPE
The General-Purpose chip select type will select the16-KByte address range from address
$4000-$7FFF.
8.2.3
A15 CHIP SELECT
The A15 chip select is address bit 15 inverted. This splits the memory map into 32K halves.
Inversion of this address bit allows it to be used directly as an active low chip select for
program memory with no additional external logic.
8.3
CONFIGURATION REGISTER (CNFGR)
The Configuration Register allows the user to program various system parameters.
Figure 8-1: Configuration Register
8.3.1
STPEN - SToP ENable
A STOP Enable bit value of logic one will enable STOP mode; a logic zero disables STOP
mode. With STOP mode disabled, execution of the Stop instruction will cause the MCU to
reset. STPEN is one-time writable. In order to write a new value, the part must first be reset
by any of the five reset conditions.
8.3.2
STREC - STop RECovery
The STOP recovery time is the number of bus cycles that elapse after STOP mode is exited
and before program operation resumes. See Figure 6-1 : Stop Recovery Timing
Diagram for more information on STOP recovery. STREC is one-time writable.
0 = 1024 cycle recovery
1 = 4064 cycle recovery
8.3.3
COPEN - Computer Operating Properly ENable
A logic one for the COPEN bit will enable the COP watchdog timer feature. See Section
information on the COP. COPEN is one-time writable.
8.3.4
IRV - Internal Read Visibility
A logic one in this bit position will turn on internal read visibility. During debugging, internal
read visibility should be on. RD and WR are active for all accesses during IRV to allow
creation of an ECLK. Enabled chip selects are active as well, and all internal bus activity is
externally visible. In normal user operation, however, IRV should be off. In this case RD,
WR, and chip selects are not active during internal accesses, preventing possible bus
LVREN
LIRV
IRV
RD
WR
1
0
RST
76543210
CNFGR
$19
STPEN
1
0
COPEN
CS1P1
CS1P0
STREC
1
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