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參數(shù)資料
| 型號(hào)： | MC68HC05C0FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 4 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 33/96頁 |
| 文件大?。?/td> | 357K |
| 代理商： | MC68HC05C0FN |
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MOTOROLA
Section 7: Input/Output Ports
Page 30
MC68HC05C0 Specification Rev. 1.2
Figure 7-1: Port D Interrupt Option
7.4
INPUT/OUTPUT PROGRAMMING
Bidirectional port lines may be programmed as an input or an output under software control.
The direction of the pins is determined by the state of the corresponding bit in the port data
direction register (DDR). Each port has an associated DDR. Any I/O port pin is configured
as an output if its corresponding DDR bit is set to a logic one. A pin is configured as an input
if its corresponding DDR bit is cleared to a logic zero.
During Reset, all DDRs are cleared, which configure all port pins as inputs. The data
direction registers are capable of being written to or read by the processor. During the
programmed output state, a read of the data register actually reads the value of the output
data latch and not the I/O pin. See Figure 7-2 : Port I/O Circuitry and Table 7-1 : I/O Pin
Table 7-1: I/O Pin Functions
NOTE:
Port lines shared with subsystems will have their direction controlled by
the subsystem if enabled, instead of the port line Data Direction Register.
However even with the subsystem enabled, during a read of the port line,
the Data Direction Register will still control from where data is read
according to Table 7-1 above (R/W = 1).
PD0
VDD
DDR Bit
Normal Port Circuitry
as shown in Figure 7-2
From all other Port D pins
To Interrupt
Logic
KSEN=0 (External Interrupt Control/Status Register)
R/W
0
1
DDR
0
1
0
1
I/O Pin Function
The I/O pin is in input mode. Data is written into the output data latch.
Data is written into the output data latch and output to the I/O pin.
The state of the I/O pin is read.
The I/O pin is in output mode. The output data latch is read.
R/W is an internal signal.
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