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參數(shù)資料
| 型號： | MC68HC05C0FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 4 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 40/96頁 |
| 文件大?。?/td> | 357K |
| 代理商： | MC68HC05C0FN |
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MOTOROLA
Section 8: System Configuration
Page 36
MC68HC05C0 Specification Rev. 1.2
Figure 8-2: External Interrupt Control/Status Register
8.4.1
KSF - Keyboard Scan request Flag
If the keyboard scan request flag is set, this indicates that a KEY request is pending. This
flag can only be set if KSEN is logic one. Writing to this bit has no effect. The KSF flag is
cleared by writing to the keyboard scan acknowledge (KSA). While servicing a KEY
interrupt, a pending interrupt request flag can be cleared by writing a logic one to the KSA
bit. In this case, if edge-level sensitive triggering is enabled, the KSEN should be cleared
as well in order to prevent re-entering the interrupt service routine.
8.4.2
KSEN - Keyboard Scan ENable
The keyboard scan feature is included to reduce external keyboard scan hardware. A logic
one enables the keyboard scan feature, which will generate a CPU interrupt if any of the
lines on the Port D pins are pulled low when their corresponding data registers are
configured as inputs. KSEN must be set in order to allow the keyboard wake-up to exit
STOP or WAIT mode.
8.4.3
Keyboard Scan Acknowledge
Writing a logic one to the KSA bit clears the keyboard scan latch. If KSEL is zero, KSF will
be cleared as well. Writing a zero has no effect. This bit always reads as zero.
8.4.4
Keyboard Scan Edge/Level
A logic one indicates edge and level sensitive triggering for a keyboard interrupt request. A
logic zero indicates falling-edge triggering only. This bit is one-time writable; in order to
write a new value, the part must first be externally reset.
8.4.5
IRQF - Interrupt ReQuest Flag
If the interrupt request flag is set, this indicates that a IRQ request is pending. The flag can
be set regardless of the state of IRQEN. Writing to this bit has no effect. The IRQF is
automatically cleared when the IRQ vector is fetched. While servicing an IRQ interrupt, a
pending interrupt request flag can be cleared by writing a logic one to the IRQA bit. In this
case, if edge-level sensitive triggering is enabled, the IRQEN should be cleared as well in
order to prevent re-entering the interrupt service routine.
8.4.6
IRQEN - Interrupt ReQuest ENable
A logic one for IRQEN enables the IRQF to initiate an IRQ interrupt sequence. If IRQEN is
a logic zero, the interrupt sequence cannot be generated, thus allowing the IRQ interrupt
to be masked without having to set the I bit to disable all interrupts. Execution of the STOP
IRQEL
IRQA
IRQEN
KSEL
KSA
RD
WR
0
1
0
RST
76543210
EICSR
$1A
0
IRQF
KSEN
KSF
0
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