參數(shù)資料
型號(hào)： MC68HC05C0FN
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 4 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 4/96頁(yè)
文件大?。?/td> 357K
代理商： MC68HC05C0FN
Section 1: Introduction
MOTOROLA
Page 3
MC68HC05C0 Specification Rev. 1.2
NOTE:
When the MCU is used in a noisy environment, it is advisable that the
Configuration Register be periodically monitored to ensure the integrity of
the programmed options.
1.4
SIGNAL DESCRIPTION
1.4.1
V
DD
AND V
SS
Power is supplied to the microcontroller using these two pins. VDD is the positive supply
and VSS is ground.
1.4.2
IRQ
This active low input-only pin is the external interrupt. The IRQ pin contains an internal
Schmitt trigger as part of its input to improve noise immunity. An External Interrupt Control/
Status Register provides a one-time writable (at reset) choice of interrupt triggering
sensitivity. This register also provides enable, request and acknowledge bits for the IRQ.
See Section 4 INTERRUPTS for more information.
1.4.3
OSC1, OSC2
These pins provide control input for an on-chip clock oscillator circuit. A crystal, a ceramic
resonator, or an external signal connects to these pins providing a system clock. The
oscillator frequency is four times the internal bus rate.
1.4.4
RESET
This active low bidirectional control pin is used as an input to reset the MCU to a known
start-up state. The RESET pin contains an internal Schmitt trigger as part of its input to
improve noise immunity. RESET is also an open-drain output to indicate that any of four
possible internal reset conditions occurred. See Section 5 RESETS for more information.
1.4.5
A15,A14-A8
These eight dedicated lines constitute the upper address byte. A15 is active low and
divides the memory map into two 32K regions. In this manner, A15 can be used as a chip
select for program memory without the need of an inverter. See Section 9 ADDRESS/
DATA BUS INTERFACE for the timing and a detailed description of the address bus.
1.4.6
AD7:0
These eight dedicated lines constitute the lower address or data byte. In Non-Muxed mode,
these eight lines become data bits D7-D0. In Muxed mode, address and data are
multiplexed together. See Section 9 ADDRESS/DATA BUS INTERFACE for the timing and
a detailed description of the address/data bus.
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