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參數(shù)資料
| 型號(hào)： | MC68HC05C0FN |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 4 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 29/96頁(yè) |
| 文件大?。?/td> | 357K |
| 代理商： | MC68HC05C0FN |
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MOTOROLA
Low-Power Modes
Page 26
MC68HC05C0 Specification Rev. 1.2
Figure 6-1: Stop Recovery Timing Diagram
6.2
WAIT
The WAIT instruction places the MCU in a low-power consumption mode, but the WAIT
mode consumes more power than the STOP mode. All CPU action is suspended in WAIT
mode. The oscillator, and the timers and SCI if enabled, remain active. Any interrupt or any
form of Reset will cause the MCU to exit the WAIT mode.
During the WAIT mode, the I bit in the CCR is cleared to enable interrupts. The IRQE bit in
the Configuration Register is set to allow an IRQ interrupt to force the MCU out of WAIT.
All other registers, memory, and input/output lines remain in their previous state.
FFFE
FFFF
INTERNAL
ADDRESS
BUS
INTERNAL
CLOCK
IRQ
3
IRQ
2
RESET
OSC1
1
t
ILCH
4064 t
cyc
RESET OR INTERRUPT
VECTOR FETCH
t
LIH
t
RL
Notes:
1. Represents the internal gating of the OSC1 pin.
2. IRQ pin edge-sensitive selection.
3. IRQ pin level and edge sensitive-selection
1024
or
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