參數(shù)資料
型號(hào)： MC68HC05C0FN
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 4 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 39/96頁(yè)
文件大?。?/td> 357K
代理商： MC68HC05C0FN
Section 8: System Configuration
MOTOROLA
Page 35
MC68HC05C0 Specification Rev. 1.2
contention. During internal accesses when IRV is off, the external address pins are driven
to the value of the last accessed external address, and the data pins (or muxed address/
data pins) are driven with the last external data. Therefore, code operating out of internal
RAM will not cause any external bus activity. This is important in reducing power
consumption and EMI emissions.
8.3.5
LIRV - Load Instruction Register Visibility
A logic one indicates that LIR will be driven as output on the LIR/MODE pin after reset. In
this case the user must ensure that the logic level on this pin, used to set bus mode, is no
longer actively driven after the rising edge of Reset. If LIRV will always be a logic zero, LIR/
MODE may be hardwired to the desired mode logic level. See Section 9 ADDRESS/DATA
BUS INTERFACE for more information on setting the mode. IRV must be set in addition to
LIRV for the LIR functionality.
8.3.6
LVREN - Low Voltage Reset ENable
A logic one enables the Low-Voltage Reset (LVR). See Section 5.3 LOW-VOLTAGE
RESET for more information.
8.3.7
CS1P1:CS1P0 - Chip Select 1 Parameters
CS1 shares a pin with the general purpose port bit PB5. The pin type and chip select type
for CS1 are determined by the value of the Chip Select Parameter bits as shown in the table
below. If CS1 is enabled, and the Page-0 type is chosen, clock stretching may be enabled
for the address range $0030 through $003F. See Section 9 ADDRESS/DATA BUS
INTERFACE for more information on clock stretching.
Table 8-1: Chip Select Types
8.4
EXTERNAL INTERRUPT CONTROL/STATUS REGISTER (EICSR)
The External Interrupt Control/Status Register provides control and status bits for the
external interrupt and the KEY interrupt.
CS1P1:CS1P0
PIN TYPE
CS1 TYPE
STRETCHING
00
Chip Select CS1
Page-0
Disabled
01
Chip Select CS1
Page-0
Enabled
10
Chip Select CS1
General Purpose
h
11
Port PB5
hh
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